nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings
There are multiple different devicetree setting formats for graphics
panel settings present in coreboot. Replace the ones for the platforms
that already have (mostly) unified gma/graphics setup code by a unified
struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt
the devicetrees accordingly.
Always ensure that values don't overflow by applying appropriate masks.
The remaining platforms implementing panel settings (GM45, i945, ILK and
SNB) can be migrated later after unifying their gma/graphics setup code.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 7adcfda..21053ec 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -243,6 +243,7 @@
static void gma_setup_panel(struct device *dev)
{
struct northbridge_intel_haswell_config *conf = config_of(dev);
+ const struct i915_gpu_panel_config *panel_cfg = &conf->panel_cfg;
u32 reg32;
/* Setup Digital Port Hotplug */
@@ -257,30 +258,30 @@
/* Setup Panel Power On Delays */
reg32 = gtt_read(PCH_PP_ON_DELAYS);
if (!reg32) {
- reg32 |= ((conf->gpu_panel_power_up_delay_ms * 10) & 0x1fff) << 16;
- reg32 |= (conf->gpu_panel_power_backlight_on_delay_ms * 10) & 0x1fff;
+ reg32 |= ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_ON_DELAYS, reg32);
}
/* Setup Panel Power Off Delays */
reg32 = gtt_read(PCH_PP_OFF_DELAYS);
if (!reg32) {
- reg32 = ((conf->gpu_panel_power_down_delay_ms * 10) & 0x1fff) << 16;
- reg32 |= (conf->gpu_panel_power_backlight_off_delay_ms * 10) & 0x1fff;
+ reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
+ reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
gtt_write(PCH_PP_OFF_DELAYS, reg32);
}
/* Setup Panel Power Cycle Delay */
- if (conf->gpu_panel_power_cycle_delay_ms) {
+ if (panel_cfg->cycle_delay_ms) {
reg32 = gtt_read(PCH_PP_DIVISOR);
reg32 &= ~0x1f;
- reg32 |= (DIV_ROUND_UP(conf->gpu_panel_power_cycle_delay_ms, 100) + 1) & 0x1f;
+ reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f;
gtt_write(PCH_PP_DIVISOR, reg32);
}
/* Enforce the PCH PWM function, as so does Linux.
The CPU PWM controls are disabled after reset. */
- if (conf->gpu_pch_backlight_pwm_hz) {
+ if (panel_cfg->backlight_pwm_hz) {
/* Reference clock is either 24MHz or 135MHz. We can choose
either a 16 or a 128 step increment. Use 16 if we would
have less than 100 steps otherwise. */
@@ -290,7 +291,7 @@
u32 south_chicken2;
south_chicken2 = gtt_read(SOUTH_CHICKEN2);
- if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
+ if (panel_cfg->backlight_pwm_hz > hz_limit) {
pwm_increment = 16;
south_chicken2 |= LPT_PWM_GRANULARITY;
} else {
@@ -299,7 +300,7 @@
}
gtt_write(SOUTH_CHICKEN2, south_chicken2);
- pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
+ pwm_period = refclock / pwm_increment / panel_cfg->backlight_pwm_hz;
printk(BIOS_INFO,
"GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n",
refclock / MHz, pwm_increment, pwm_period,
@@ -309,7 +310,7 @@
gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
gtt_write(BLC_PWM_PCH_CTL1,
- (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
+ (panel_cfg->backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE);
}