mainboard/google/kahlee: Add tis_plat_irq_status
For variants that have a cr50 tpm, this enables faster polling when
interacting with the tpm.
BUG=b:72838769
BRANCH=none
TEST=verified on grunt that irq is used and not timeouts for tpm
Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 244abe0..4a65d8f 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -15,8 +15,10 @@
#include <baseboard/variants.h>
#include <bootblock_common.h>
+#include <soc/gpio.h>
#include <soc/southbridge.h>
#include <variant/ec.h>
+#include <variant/gpio.h>
void bootblock_mainboard_init(void)
{
@@ -30,4 +32,11 @@
/* Setup TPM decode before verstage */
sb_tpm_decode_spi();
+
+ /* Configure cr50 interrupt pin for use in polling tpm status */
+ if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) {
+ const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW |
+ GPIO_INT_STATUS_EN;
+ gpio_set_interrupt(H1_PCH_INT, flags);
+ }
}
diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
index fcaf365..c4c2f9d 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
@@ -1,7 +1,7 @@
#
# This file is part of the coreboot project.
#
-# Copyright (C) 2017 Google, Inc.
+# Copyright (C) 2018 Google, LLC.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -16,7 +16,11 @@
bootblock-y += gpio.c
bootblock-y += OemCustomize.c
+verstage-y += tpm_tis.c
+
romstage-y += gpio.c
romstage-y += memory.c
+romstage-y += tpm_tis.c
ramstage-y += gpio.c
+ramstage-y += tpm_tis.c
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
index e237ce2..1e349b7 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
@@ -24,6 +24,9 @@
# define MEM_CONFIG2 GPIO_131
# define MEM_CONFIG3 GPIO_132
+/* CR50 interrupt pin */
+#define H1_PCH_INT GPIO_9
+
/* SPI Write protect */
#define CROS_WP_GPIO GPIO_122
#define GPIO_EC_IN_RW GPIO_15
diff --git a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c
new file mode 100644
index 0000000..fe5e42c
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <security/tpm/tis.h>
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+int tis_plat_irq_status(void)
+{
+ return gpio_interrupt_status(H1_PCH_INT);
+}
diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
index 21b14c5..26dd175 100644
--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
+++ b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
@@ -28,6 +28,9 @@
#define MEM_CONFIG2 0
#define MEM_CONFIG3 0
+/* CDX03 doesn't have a CR50 interrupt pin */
+#define H1_PCH_INT 0
+
/* SPI Write protect */
#define CROS_WP_GPIO GPIO_142
#define GPIO_EC_IN_RW GPIO_15