diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index afbade4c1..925c60c 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -30,7 +30,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
-#include <cpu/amd/pi/s3_resume.h>
 
 static void model_15_init(device_t dev)
 {
@@ -65,9 +64,6 @@
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
-		restore_mtrr();
-
 	x86_mtrr_check();
 	x86_enable_cache();
 
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index e252c3d..c31dec8 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -29,7 +29,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
-#include <cpu/amd/pi/s3_resume.h>
 
 #include <amdlib.h>
 #include <PspBaseLib.h>
@@ -80,9 +79,6 @@
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
-		restore_mtrr();
-
 	x86_mtrr_check();
 	x86_enable_cache();
 
diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c
index dd1c8e3..02e5b79 100644
--- a/src/cpu/amd/pi/00670F00/model_15_init.c
+++ b/src/cpu/amd/pi/00670F00/model_15_init.c
@@ -29,7 +29,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam15.h>
 #include <arch/acpi.h>
-#include <cpu/amd/pi/s3_resume.h>
 
 #include <amdlib.h>
 #include <PspBaseLib.h>
@@ -80,9 +79,6 @@
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
-		restore_mtrr();
-
 	x86_mtrr_check();
 	x86_enable_cache();
 
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index a9751a2..294814f 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -29,7 +29,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/amdfam16.h>
 #include <arch/acpi.h>
-#include <cpu/amd/pi/s3_resume.h>
 
 static void model_16_init(device_t dev)
 {
@@ -63,9 +62,6 @@
 	msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
 	wrmsr(SYSCFG_MSR, msr);
 
-	if (acpi_is_wakeup())
-		restore_mtrr();
-
 	x86_mtrr_check();
 	x86_enable_cache();
 
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index 0e31d9f..3dcbbc3 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -18,8 +18,6 @@
 subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00
 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
 
-romstage-y += s3_resume.c
-ramstage-y += s3_resume.c
 ramstage-$(CONFIG_SPI_FLASH) += spi.c
 
 cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc
@@ -27,18 +25,3 @@
 romstage-y += heapmanager.c
 ramstage-y += heapmanager.c
 ramstage-y += amd_late_init.c
-
-ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
-
-$(obj)/coreboot_s3nv.rom: $(obj)/config.h
-	echo "    S3 NVRAM   $(CONFIG_S3_DATA_POS) (S3 storage area)"
-	# force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse)
-	printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp
-	mv $@.tmp $@
-
-cbfs-files-y += s3nv
-s3nv-file := $(obj)/coreboot_s3nv.rom
-s3nv-position := $(CONFIG_S3_DATA_POS)
-s3nv-type := raw
-
-endif # CONFIG_HAVE_ACPI_RESUME == y
diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c
deleted file mode 100644
index 338f921..0000000
--- a/src/cpu/amd/pi/s3_resume.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <AGESA.h>
-#include <Lib/amdlib.h>
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cbmem.h>
-#include <device/device.h>
-#include <arch/io.h>
-#include <arch/acpi.h>
-#include <program_loading.h>
-#include <string.h>
-#include "Porting.h"
-#include <northbridge/amd/pi/BiosCallOuts.h>
-#include <halt.h>
-#include "s3_resume.h"
-
-/* The size needs to be 4k aligned, which is the sector size of most flashes. */
-#define S3_DATA_VOLATILE_SIZE		0x6000
-#define S3_DATA_MTRR_SIZE		0x1000
-#define S3_DATA_NONVOLATILE_SIZE	0x1000
-
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
-	(S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE
-#error "Please increase the value of S3_DATA_SIZE"
-#endif
-
-static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
-{
-	/* FIXME: Find file from CBFS. */
-	u32 s3_data = CONFIG_S3_DATA_POS;
-
-	switch (S3DataType) {
-	case S3DataTypeVolatile:
-		*pos = s3_data;
-		*len = S3_DATA_VOLATILE_SIZE;
-		break;
-	case S3DataTypeMTRR:
-		*pos = s3_data + S3_DATA_VOLATILE_SIZE;
-		*len = S3_DATA_MTRR_SIZE;
-		break;
-	case S3DataTypeNonVolatile:
-		*pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE;
-		*len = S3_DATA_NONVOLATILE_SIZE;
-		break;
-	default:
-		*pos = 0;
-		*len = 0;
-		break;
-	}
-}
-
-void restore_mtrr(void)
-{
-	u32 msr;
-	volatile UINT32 *msrPtr;
-	msr_t msr_data;
-
-	printk(BIOS_SPEW, "%s\n", __func__);
-
-	u32 pos, size;
-	get_s3nv_data(S3DataTypeMTRR, &pos, &size);
-	msrPtr = (UINT32 *)(pos + sizeof(UINT32));
-
-	disable_cache();
-
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYS_CFG);
-	msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYS_CFG, msr_data);
-
-	/* Now restore the Fixed MTRRs */
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(0x250, msr_data);
-
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(0x258, msr_data);
-
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(0x259, msr_data);
-
-	for (msr = 0x268; msr <= 0x26F; msr++) {
-		msr_data.lo = *msrPtr;
-		msrPtr ++;
-		msr_data.hi = *msrPtr;
-		msrPtr ++;
-		wrmsr(msr, msr_data);
-	}
-
-	/* Disable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYS_CFG);
-	msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYS_CFG, msr_data);
-
-	/* Restore the Variable MTRRs */
-	for (msr = 0x200; msr <= 0x20F; msr++) {
-		msr_data.lo = *msrPtr;
-		msrPtr ++;
-		msr_data.hi = *msrPtr;
-		msrPtr ++;
-		wrmsr(msr, msr_data);
-	}
-
-	/* Restore SYSCFG MTRR */
-	msr_data.lo = *msrPtr;
-	msrPtr ++;
-	msr_data.hi = *msrPtr;
-	msrPtr ++;
-	wrmsr(SYS_CFG, msr_data);
-}
-
-#ifdef __PRE_RAM__
-static void move_stack_high_mem(void)
-{
-	uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE,
-		ROMSTAGE_STACK_CBMEM);
-	if (!high_stack)
-		halt();
-
-	/* TODO: Make the switch with empty stack instead. */
-	memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
-
-#ifdef __x86_64__
-	__asm__
-	    volatile ("add	%0, %%rsp; add %0, %%rbp; invd"::"g"
-		      (high_stack - BSP_STACK_BASE_ADDR)
-		      :);
-#else
-	__asm__
-	    volatile ("add	%0, %%esp; add %0, %%ebp; invd"::"g"
-		      (high_stack - BSP_STACK_BASE_ADDR)
-		      :);
-#endif
-}
-#endif
-
-#ifndef __PRE_RAM__
-/* FIXME: Why store MTRR in SPI, just use CBMEM ? */
-static u8 mtrr_store[S3_DATA_MTRR_SIZE];
-
-static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
-{
-	msr_t  msr_data;
-	msr_data = rdmsr(idx);
-
-	memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data));
-	*p_nvram_pos += sizeof(msr_data);
-}
-
-void OemAgesaSaveMtrr(void)
-{
-	msr_t  msr_data;
-	u32 i;
-
-	u8 *nvram_pos = (u8 *) mtrr_store;
-
-	/* Enable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYS_CFG);
-	msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYS_CFG, msr_data);
-
-	/* Fixed MTRRs */
-	write_mtrr(&nvram_pos, 0x250);
-	write_mtrr(&nvram_pos, 0x258);
-	write_mtrr(&nvram_pos, 0x259);
-
-	for (i = 0x268; i < 0x270; i++)
-		write_mtrr(&nvram_pos, i);
-
-	/* Disable access to AMD RdDram and WrDram extension bits */
-	msr_data = rdmsr(SYS_CFG);
-	msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYS_CFG, msr_data);
-
-	/* Variable MTRRs */
-	for (i = 0x200; i < 0x210; i++)
-		write_mtrr(&nvram_pos, i);
-
-	/* SYS_CFG */
-	write_mtrr(&nvram_pos, 0xC0010010);
-	/* TOM */
-	write_mtrr(&nvram_pos, 0xC001001A);
-	/* TOM2 */
-	write_mtrr(&nvram_pos, 0xC001001D);
-
-#if IS_ENABLED(CONFIG_SPI_FLASH)
-	u32 pos, size;
-	get_s3nv_data(S3DataTypeMTRR, &pos, &size);
-	spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store);
-#endif
-}
-
-u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
-{
-#if IS_ENABLED(CONFIG_SPI_FLASH)
-	u32 pos, size;
-	get_s3nv_data(S3DataType, &pos, &size);
-	spi_SaveS3info(pos, size, Data, DataSize);
-#endif
-	return AGESA_SUCCESS;
-}
-#endif
-
-void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data)
-{
-	AMD_CONFIG_PARAMS StdHeader;
-
-	u32 pos, size;
-	get_s3nv_data(S3DataType, &pos, &size);
-
-	if (S3DataType == S3DataTypeNonVolatile) {
-		*DataSize = *(UINT32 *) pos;
-		*Data = (void *) (pos + sizeof(UINT32));
-	} else if (S3DataType == S3DataTypeVolatile) {
-		u32 len = *(UINT32 *) pos;
-		void *src = (void *) (pos + sizeof(UINT32));
-		void *dst = (void *) GetHeapBase(&StdHeader);
-		memcpy(dst, src, len);
-		*DataSize = len;
-		*Data = dst;
-	}
-}
-
-#ifdef __PRE_RAM__
-static void set_resume_cache(void)
-{
-	msr_t msr;
-
-	/* disable fixed mtrr for now,  it will be enabled by mtrr restore */
-	msr = rdmsr(SYSCFG_MSR);
-	msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
-	wrmsr(SYSCFG_MSR, msr);
-
-	/* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */
-	msr.lo = 0 | MTRR_TYPE_WRBACK;
-	msr.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(0), msr);
-	msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID;
-	msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(0), msr);
-
-	/* Set the default memory type and disable fixed and enable variable MTRRs */
-	msr.hi = 0;
-	msr.lo = (1 << 11);
-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
-
-	enable_cache();
-}
-
-void prepare_for_resume(void)
-{
-	if (cbmem_recovery(1)) {
-		printk(BIOS_EMERG, "Unable to recover CBMEM\n");
-		halt();
-	}
-
-	post_code(0x62);
-	printk(BIOS_DEBUG, "Move CAR stack.\n");
-	move_stack_high_mem();
-
-	post_code(0x63);
-	disable_cache_as_ram();
-	printk(BIOS_DEBUG, "CAR disabled.\n");
-	set_resume_cache();
-
-}
-#endif
diff --git a/src/cpu/amd/pi/s3_resume.h b/src/cpu/amd/pi/s3_resume.h
deleted file mode 100644
index c23c662..0000000
--- a/src/cpu/amd/pi/s3_resume.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef S3_RESUME_H
-#define S3_RESUME_H
-
-typedef enum {
-	S3DataTypeNonVolatile=0,	///< NonVolatile Data Type
-	S3DataTypeVolatile,		///< Volatile Data Type
-	S3DataTypeMTRR			///< MTRR storage
-} S3_DATA_TYPE;
-
-void restore_mtrr(void);
-void prepare_for_resume(void);
-
-u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data);
-void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data);
-void OemAgesaSaveMtrr (void);
-
-void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len);
-
-/* This covers node 0 only. */
-#define HIGH_ROMSTAGE_STACK_SIZE	(0x48000 - BSP_STACK_BASE_ADDR)
-
-#endif
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 2e79f47..213d784 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -16,7 +16,6 @@
 #include <AGESA.h>
 #include <cbfs.h>
 #include <delay.h>
-#include <cpu/amd/pi/s3_resume.h>
 #include <cpu/x86/mtrr.h>
 #include <cpuRegisters.h>
 #include <FchPlatform.h>
@@ -24,9 +23,6 @@
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/BiosCallOuts.h>
 
-VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
-VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
-
 void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {}
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
@@ -368,215 +364,6 @@
 	return Status;
 }
 
-#if CONFIG_HAVE_ACPI_RESUME
-
-AGESA_STATUS agesawrapper_amdinitresume(void)
-{
-	AGESA_STATUS status;
-	AMD_INTERFACE_PARAMS AmdParamStruct;
-	AMD_RESUME_PARAMS     *AmdResumeParamsPtr;
-	S3_DATA_TYPE            S3DataType;
-
-	LibAmdMemFill (&AmdParamStruct,
-		       0,
-		       sizeof(AMD_INTERFACE_PARAMS),
-		       &(AmdParamStruct.StdHeader));
-
-	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
-	AmdParamStruct.AllocationMethod = PreMemHeap;
-	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-	AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdParamStruct.StdHeader.Func = 0;
-	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct (&AmdParamStruct);
-
-	AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
-
-	AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
-	AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
-	S3DataType = S3DataTypeNonVolatile;
-	OemAgesaGetS3Info (S3DataType,
-			   (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
-			   (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
-
-	status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
-
-	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
-	AmdReleaseStruct (&AmdParamStruct);
-
-	return status;
-}
-
-#ifndef __PRE_RAM__
-AGESA_STATUS agesawrapper_fchs3earlyrestore(void)
-{
-	AGESA_STATUS status = AGESA_SUCCESS;
-
-	FCH_DATA_BLOCK      FchParams;
-	AMD_CONFIG_PARAMS StdHeader;
-
-	StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
-	StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
-	StdHeader.AltImageBasePtr = 0;
-	StdHeader.CalloutPtr = &GetBiosCallout;
-	StdHeader.Func = 0;
-	StdHeader.ImageBasePtr = 0;
-
-	LibAmdMemFill (&FchParams,
-		       0,
-		       sizeof(FchParams),
-		       &StdHeader);
-
-	FchParams.StdHeader = &StdHeader;
-	s3_resume_init_data(&FchParams);
-
-	FchInitS3EarlyRestore(&FchParams);
-
-	return status;
-}
-#endif /* #ifndef __PRE_RAM__ */
-
-AGESA_STATUS agesawrapper_amds3laterestore(void)
-{
-	AGESA_STATUS Status;
-	AMD_INTERFACE_PARAMS    AmdInterfaceParams;
-	AMD_S3LATE_PARAMS       AmdS3LateParams;
-	AMD_S3LATE_PARAMS       *AmdS3LateParamsPtr;
-	S3_DATA_TYPE          S3DataType;
-
-	agesawrapper_amdinitcpuio();
-	LibAmdMemFill (&AmdS3LateParams,
-		       0,
-		       sizeof(AMD_S3LATE_PARAMS),
-		       &(AmdS3LateParams.StdHeader));
-	AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
-	AmdInterfaceParams.AllocationMethod = ByHost;
-	AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
-	AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
-	AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdS3LateParamsPtr = &AmdS3LateParams;
-	AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS);
-
-	AmdCreateStruct (&AmdInterfaceParams);
-
-	AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
-	S3DataType = S3DataTypeVolatile;
-
-	OemAgesaGetS3Info (S3DataType,
-			   (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
-			   (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
-
-	Status = AmdS3LateRestore (AmdS3LateParamsPtr);
-	if (Status != AGESA_SUCCESS) {
-		agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus);
-		ASSERT(Status == AGESA_SUCCESS);
-	}
-
-	return Status;
-}
-
-#ifndef __PRE_RAM__
-
-AGESA_STATUS agesawrapper_fchs3laterestore(void)
-{
-	AGESA_STATUS status = AGESA_SUCCESS;
-
-	AMD_CONFIG_PARAMS       StdHeader;
-	FCH_DATA_BLOCK          FchParams;
-
-	StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
-	StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
-	StdHeader.AltImageBasePtr = 0;
-	StdHeader.CalloutPtr = &GetBiosCallout;
-	StdHeader.Func = 0;
-	StdHeader.ImageBasePtr = 0;
-
-	LibAmdMemFill (&FchParams,
-		       0,
-		       sizeof(FchParams),
-		       &StdHeader);
-
-	FchParams.StdHeader = &StdHeader;
-	s3_resume_init_data(&FchParams);
-	FchInitS3LateRestore(&FchParams);
-
-	/* PIC IRQ routine */
-	for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
-		outb(byte, 0xC00);
-		outb(picr_data[byte], 0xC01);
-	}
-
-	/* APIC IRQ routine */
-	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-		outb(byte | 0x80, 0xC00);
-		outb(intr_data[byte], 0xC01);
-	}
-
-	return status;
-}
-
-AGESA_STATUS agesawrapper_amdS3Save(void)
-{
-	AGESA_STATUS Status;
-	AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
-	AMD_INTERFACE_PARAMS  AmdInterfaceParams;
-	S3_DATA_TYPE          S3DataType;
-
-	LibAmdMemFill (&AmdInterfaceParams,
-		       0,
-		       sizeof(AMD_INTERFACE_PARAMS),
-		       &(AmdInterfaceParams.StdHeader));
-
-	AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
-	AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
-	AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdInterfaceParams.AllocationMethod = PostMemDram;
-	AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
-	AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
-	AmdInterfaceParams.StdHeader.Func = 0;
-
-	AmdCreateStruct(&AmdInterfaceParams);
-	AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
-	AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
-
-	Status = AmdS3Save(AmdS3SaveParamsPtr);
-	if (Status != AGESA_SUCCESS) {
-		agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus);
-		ASSERT(Status == AGESA_SUCCESS);
-	}
-
-	S3DataType = S3DataTypeNonVolatile;
-	printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n",
-	       (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
-	       (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
-
-	Status = OemAgesaSaveS3Info (
-		S3DataType,
-		AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
-		AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
-
-	printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
-	       (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
-	       (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
-
-	if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
-		S3DataType = S3DataTypeVolatile;
-
-		Status = OemAgesaSaveS3Info (
-			S3DataType,
-			AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
-			AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
-	}
-	OemAgesaSaveMtrr();
-
-	AmdReleaseStruct (&AmdInterfaceParams);
-
-	return Status;
-}
-
-#endif  /* #ifndef __PRE_RAM__ */
-#endif  /* CONFIG_HAVE_ACPI_RESUME */
-
 AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus)
 {
 	AGESA_STATUS Status;