mb/system76/adl: Add Gazelle 17 as a variant
The gaze17 comes in 2 variants due to differences in the discrete GPU
and network controller used.
- NVIDIA RTX 3050, using Realtek Ethernet Controller
- NVIDIA RTX 3060, using onboard I219-V Ethernet Controller
Tested with a custom TianoCore UefiPayloadPkg payload.
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe SSD
- M.2 SATA SSD
- MicroSD card reader
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S0ix suspend/resume
- Booting to Pop!_OS Linux 22.04 with kernel 6.2.6
- Internal flashing with flashrom v1.2-703-g76118a7c10ed
Not working:
- Discrete/Hybrid graphics: Requires NVIDIA driver
- mDP/HDMI displays on 3060 variant: Requires NVIDIA driver
- Detection of devices in TBT slot on boot
- S3 suspend: MP init eventually fails
Not tested:
- Thunderbolt devices
Change-Id: Ib12ac47e8f34004f72e6234039823530511baea7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 59e91d4..06c60cb 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -214,6 +214,7 @@
- [Galago Pro 6](system76/galp6.md)
- [Gazelle 15](system76/gaze15.md)
- [Gazelle 16](system76/gaze16.md)
+- [Gazelle 17](system76/gaze17.md)
- [Gazelle 18](system76/gaze18.md)
- [Lemur Pro 9](system76/lemp9.md)
- [Lemur Pro 10](system76/lemp10.md)
diff --git a/Documentation/mainboard/system76/gaze17.md b/Documentation/mainboard/system76/gaze17.md
new file mode 100644
index 0000000..cf7f0a2
--- /dev/null
+++ b/Documentation/mainboard/system76/gaze17.md
@@ -0,0 +1,65 @@
+# System76 Gazelle 17 (gaze17)
+
+The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
+
+## Specs
+
+- CPU
+ - Intel Core i5-12500H
+ - Intel Core i7-12700H
+- EC
+ - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+ - dGPU options
+ - NVIDIA GeForce RTX 3050
+ - NVIDIA GeForce RTX 3050 Ti
+ - NVIDIA GeForce RTX 3060
+- Memory
+ - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
+- Networking
+ - Gigabit Ethernet
+ - 3050: Realtek RTL8111H controller
+ - 3060: Onboard Intel I219-V
+ - M.2 PCIe/CNVi WiFi/Bluetooth
+ - Intel Wi-Fi 6 AX201
+- Power
+ - 3050: 150W (20V, 7.5A) AC barrel adapter
+ - 3060: 180W (20V, 9A) AC barrel adapter
+ - Lite-On PA-1181-76, using a C5 power cord
+ - 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
+- Sound
+ - Realtek ALC256 codec
+ - Internal speakers and microphone
+ - Combined 3.5mm headphone/microphone jack
+ - Dedicated 3.5mm microphone jack
+- Storage
+ - 1x M.2 PCIe NVMe Gen 4 SSD
+ - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
+ - MicroSD card reader (Realtek RTS5227S/OZ711LV2)
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+---------------------+
+| Type | Value |
++=====================+=====================+
+| Socketed flash | no |
++---------------------+---------------------+
+| Vendor | GigaDevice |
++---------------------+---------------------+
+| Model | GD25B256E |
++---------------------+---------------------+
+| Size | 32 MiB |
++---------------------+---------------------+
+| Package | WSON-8 |
++---------------------+---------------------+
+| Internal flashing | yes |
++---------------------+---------------------+
+| External flashing | yes |
++---------------------+---------------------+
+```
+
+The position of the flash chip depends on the variant:
+
+- 3050: U24, below the bottom DIMM slot.
+- 3060: U55, left of the PCIe 4.0 M.2 slot.
diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig
index 83176d1..e505ebb 100644
--- a/src/mainboard/system76/adl/Kconfig
+++ b/src/mainboard/system76/adl/Kconfig
@@ -1,19 +1,13 @@
-if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
+config BOARD_SYSTEM76_ADL_COMMON
+ def_bool n
select BOARD_ROMSIZE_KB_32768
select DRIVERS_I2C_HID
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_USB4_RETIMER
- select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP9
select EC_SYSTEM76_EC
- select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
- select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
- select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP11
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_TPM2
@@ -26,12 +20,49 @@
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
+config BOARD_SYSTEM76_DARP8
+ select BOARD_SYSTEM76_ADL_COMMON
+ select EC_SYSTEM76_EC_COLOR_KEYBOARD
+
+config BOARD_SYSTEM76_GALP6
+ select BOARD_SYSTEM76_ADL_COMMON
+
+config BOARD_SYSTEM76_GAZE17_3050
+ select BOARD_SYSTEM76_ADL_COMMON
+ select EC_SYSTEM76_EC_COLOR_KEYBOARD
+ select EC_SYSTEM76_EC_DGPU
+
+config BOARD_SYSTEM76_GAZE17_3060_B
+ select BOARD_SYSTEM76_ADL_COMMON
+ select EC_SYSTEM76_EC_COLOR_KEYBOARD
+ select EC_SYSTEM76_EC_DGPU
+ select MAINBOARD_USES_IFD_GBE_REGION
+
+config BOARD_SYSTEM76_LEMP11
+ select BOARD_SYSTEM76_ADL_COMMON
+ select HAVE_SPD_IN_CBFS
+
+config BOARD_SYSTEM76_ORYP9
+ select BOARD_SYSTEM76_ADL_COMMON
+ select DRIVERS_I2C_TAS5825M
+ select EC_SYSTEM76_EC_COLOR_KEYBOARD
+ select EC_SYSTEM76_EC_DGPU
+
+config BOARD_SYSTEM76_ORYP10
+ select BOARD_SYSTEM76_ADL_COMMON
+ select EC_SYSTEM76_EC_COLOR_KEYBOARD
+ select EC_SYSTEM76_EC_DGPU
+
+if BOARD_SYSTEM76_ADL_COMMON
+
config MAINBOARD_DIR
default "system76/adl"
config VARIANT_DIR
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
+ default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
+ default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
default "lemp11" if BOARD_SYSTEM76_LEMP11
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10
@@ -42,6 +73,8 @@
config MAINBOARD_PART_NUMBER
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
+ default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
+ default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
default "lemp11" if BOARD_SYSTEM76_LEMP11
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10
@@ -49,12 +82,15 @@
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Darter Pro" if BOARD_SYSTEM76_DARP8
default "Galago Pro" if BOARD_SYSTEM76_GALP6
+ default "Gazelle" if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B
default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
config MAINBOARD_VERSION
default "darp8" if BOARD_SYSTEM76_DARP8
default "galp6" if BOARD_SYSTEM76_GALP6
+ default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
+ default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
default "lemp11" if BOARD_SYSTEM76_LEMP11
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10
diff --git a/src/mainboard/system76/adl/Kconfig.name b/src/mainboard/system76/adl/Kconfig.name
index ee7b6ff..99d7ea0 100644
--- a/src/mainboard/system76/adl/Kconfig.name
+++ b/src/mainboard/system76/adl/Kconfig.name
@@ -4,6 +4,12 @@
config BOARD_SYSTEM76_GALP6
bool "galp6"
+config BOARD_SYSTEM76_GAZE17_3050
+ bool "gaze17 3050"
+
+config BOARD_SYSTEM76_GAZE17_3060_B
+ bool "gaze17 3060-b"
+
config BOARD_SYSTEM76_LEMP11
bool "lemp11"
diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/board_info.txt b/src/mainboard/system76/adl/variants/gaze17-3050/board_info.txt
new file mode 100644
index 0000000..926fe4e
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3050/board_info.txt
@@ -0,0 +1,2 @@
+Board name: gaze17-3050
+Release year: 2022
diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/data.vbt b/src/mainboard/system76/adl/variants/gaze17-3050/data.vbt
new file mode 100644
index 0000000..c0531fd
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3050/data.vbt
Binary files differ
diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/gpio.c b/src/mainboard/system76/adl/variants/gaze17-3050/gpio.c
new file mode 100644
index 0000000..a30eec1
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3050/gpio.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+ /* ------- GPIO Group GPD ------- */
+ PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+ PAD_CFG_GPO(GPD7, 0, DEEP), // GPD7_REST
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+ PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LANPHYPC
+
+ /* ------- GPIO Group GPP_A ------- */
+ PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+ PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+ PAD_NC(GPP_A6, NONE),
+ PAD_NC(GPP_A7, NONE),
+ PAD_CFG_GPO(GPP_A8, 1, PLTRST), // SATA_PWR_EN
+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
+ PAD_NC(GPP_A11, NONE),
+ PAD_NC(GPP_A12, NONE),
+ PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
+ //PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14
+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // PCH_DP_HPD
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
+ PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
+ PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH
+ PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE#
+ PAD_NC(GPP_A21, NONE),
+ PAD_NC(GPP_A22, NONE),
+ PAD_NC(GPP_A23, NONE),
+
+ /* ------- GPIO Group GPP_B ------- */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+ //PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+ PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+ PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+ PAD_NC(GPP_B5, NONE),
+ PAD_NC(GPP_B6, NONE),
+ PAD_CFG_GPO(GPP_B7, 1, DEEP), // CARD_PWR_EN
+ PAD_CFG_GPO(GPP_B8, 1, DEEP), // CARD_RTD3_RST#
+ //PAD_NC(GPP_B9, NONE),
+ //PAD_NC(GPP_B10, NONE),
+ PAD_NC(GPP_B11, NONE),
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+ _PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED#
+ PAD_NC(GPP_B15, NONE),
+ PAD_NC(GPP_B16, NONE),
+ PAD_NC(GPP_B17, NONE),
+ PAD_CFG_GPO(GPP_B18, 0, DEEP), // GPP_B18_STRAP
+ //PAD_NC(GPP_B19, NONE),
+ //PAD_NC(GPP_B20, NONE),
+ //PAD_NC(GPP_B21, NONE),
+ //PAD_NC(GPP_B22, NONE),
+ PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23_STRAP
+
+ /* ------- GPIO Group GPP_C ------- */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+ PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
+ PAD_NC(GPP_C3, NONE), // SML0_CLK
+ PAD_NC(GPP_C4, NONE), // SML0_DATA
+ PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C5_STRAP
+ PAD_NC(GPP_C6, NONE), // TBT_I2C_SCL
+ PAD_NC(GPP_C7, NONE), // TBT_I2C_SDA
+ //PAD_NC(GPP_C8, NONE),
+ //PAD_NC(GPP_C9, NONE),
+ //PAD_NC(GPP_C10, NONE),
+ //PAD_NC(GPP_C11, NONE),
+ //PAD_NC(GPP_C12, NONE),
+ //PAD_NC(GPP_C13, NONE),
+ //PAD_NC(GPP_C14, NONE),
+ //PAD_NC(GPP_C15, NONE),
+ //PAD_NC(GPP_C16, NONE),
+ //PAD_NC(GPP_C17, NONE),
+ //PAD_NC(GPP_C18, NONE),
+ //PAD_NC(GPP_C19, NONE),
+ //PAD_NC(GPP_C20, NONE),
+ //PAD_NC(GPP_C21, NONE),
+ //PAD_NC(GPP_C22, NONE),
+ //PAD_NC(GPP_C23, NONE),
+
+ /* ------- GPIO Group GPP_D ------- */
+ PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+ PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+ PAD_NC(GPP_D2, NONE),
+ PAD_NC(GPP_D3, NONE),
+ PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN
+ //PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
+ //PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
+ //PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+ //PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
+ PAD_NC(GPP_D9, NONE),
+ PAD_NC(GPP_D10, NONE),
+ PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK
+ PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2), // I_MDP_DATA
+ PAD_NC(GPP_D13, NONE),
+ PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
+ PAD_CFG_GPO(GPP_D15, 1, DEEP), // LANRTD3_WAKE#
+ PAD_CFG_GPO(GPP_D16, 1, PLTRST), // LAN_RTD3_EN#
+ PAD_NC(GPP_D17, NONE),
+ PAD_NC(GPP_D18, NONE),
+ PAD_NC(GPP_D19, NONE),
+
+ /* ------- GPIO Group GPP_E ------- */
+ PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+ //_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
+ PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
+ PAD_NC(GPP_E4, NONE),
+ PAD_NC(GPP_E5, NONE),
+ PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6_STRAP
+ PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+ PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+ PAD_CFG_GPO(GPP_E10, 0, DEEP), // KBLED_DET
+ PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+ PAD_NC(GPP_E12, NONE),
+ PAD_CFG_GPO(GPP_E13, 0, DEEP), // BOARD_ID4
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+ PAD_NC(GPP_E15, NONE),
+ PAD_NC(GPP_E16, NONE),
+ PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3
+ PAD_NC(GPP_E18, NONE),
+ PAD_NC(GPP_E19, NONE), // GPP_E19_STRAP
+ PAD_NC(GPP_E20, NONE),
+ PAD_NC(GPP_E21, NONE),
+ PAD_NC(GPP_E22, NONE), // GPP_E21_STRAP
+ PAD_NC(GPP_E23, NONE),
+
+ /* ------- GPIO Group GPP_F ------- */
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+ PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+ //PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
+ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+ PAD_NC(GPP_F7, NONE),
+ //PAD_NC(GPP_F8, NONE),
+ PAD_NC(GPP_F9, NONE),
+ PAD_CFG_GPO(GPP_F10, 1, DEEP), // PCIE_GLAN_RST#
+ PAD_NC(GPP_F11, NONE), // ADDS_CODE
+ PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
+ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
+ PAD_NC(GPP_F14, NONE), // LIGHT_KB_DET#
+ PAD_NC(GPP_F15, NONE),
+ PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
+ PAD_NC(GPP_F17, NONE),
+ PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM
+ //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ#
+ PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
+ PAD_NC(GPP_F21, NONE),
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL
+ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), // V1P05_CTRL
+
+ /* ------- GPIO Group GPP_H ------- */
+ PAD_NC(GPP_H0, NONE),
+ PAD_CFG_GPO(GPP_H1, 1, DEEP), // M.2_PLT_RST_CNTRL2#
+ PAD_CFG_GPO(GPP_H2, 1, DEEP), // M.2_PLT_RST_CNTRL3#
+ PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+ PAD_CFG_GPI(GPP_H6, NONE, DEEP), // PCH_I2C_SDA
+ PAD_CFG_GPI(GPP_H7, NONE, DEEP), // PCH_I2C_SCL
+ PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
+ PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
+ //PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+ //PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+ PAD_NC(GPP_H12, NONE),
+ _PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1
+ //PAD_NC(GPP_H14, NONE),
+ PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
+ //PAD_NC(GPP_H16, NONE),
+ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+ PAD_NC(GPP_H19, NONE),
+ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // PM_CLKRUN#
+ PAD_NC(GPP_H21, NONE),
+ PAD_NC(GPP_H22, NONE),
+ //PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
+
+ /* ------- GPIO Group GPP_R ------- */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+ PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+ PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT_L
+ PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+ PAD_NC(GPP_R5, NONE),
+ PAD_CFG_GPO(GPP_R6, 0, DEEP), // GPPR_DMIC_CLK
+ PAD_CFG_GPO(GPP_R7, 0, DEEP), // GPPR_DMIC_DATA
+
+ /* ------- GPIO Group GPP_S ------- */
+ PAD_NC(GPP_S0, NONE),
+ PAD_NC(GPP_S1, NONE),
+ PAD_NC(GPP_S2, NONE),
+ PAD_NC(GPP_S3, NONE),
+ PAD_NC(GPP_S4, NONE),
+ PAD_NC(GPP_S5, NONE),
+ PAD_NC(GPP_S6, NONE),
+ PAD_NC(GPP_S7, NONE),
+
+ /* ------- GPIO Group GPP_T ------- */
+ PAD_NC(GPP_T2, NONE),
+ PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c b/src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c
new file mode 100644
index 0000000..85b9307
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3050/gpio_early.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+ PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+ PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c b/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c
new file mode 100644
index 0000000..337f469
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* Realtek, ALC256 */
+ 0x10ec0256, /* Vendor ID */
+ 0x1558866d, /* Subsystem ID */
+ 12, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x1558866d),
+ AZALIA_RESET(1),
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+ AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {
+ // Adjust mic coefficient
+ 0x02050007,
+ 0x02040202,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb
new file mode 100644
index 0000000..174c926
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb
@@ -0,0 +1,154 @@
+chip soc/intel/alderlake
+ # FIVR configuration
+ # Read EXT_RAIL_CONFIG to determine bitmaps
+ # sudo devmem2 0xfe0011b8
+ # 0x0
+ # Read EXT_V1P05_VR_CONFIG
+ # sudo devmem2 0xfe0011c0
+ # 0x1a42000
+ # Read EXT_VNN_VR_CONFIG0
+ # sudo devmem2 0xfe0011c4
+ # 0x1a42000
+ # TODO: v1p05 voltage and vnn icc max?
+ register "ext_fivr_settings" = "{
+ .configure_ext_fivr = 1,
+ .v1p05_enable_bitmap = 0,
+ .vnn_enable_bitmap = 0,
+ .v1p05_supported_voltage_bitmap = 0,
+ .vnn_supported_voltage_bitmap = 0,
+ .v1p05_icc_max_ma = 500,
+ .vnn_sx_voltage_mv = 1050,
+ }"
+
+ # Thermal
+ register "tcc_offset" = "10"
+
+ # GPE configuration
+ register "pmc_gpe0_dw0" = "PMC_GPP_R"
+ register "pmc_gpe0_dw1" = "PMC_GPP_B"
+ register "pmc_gpe0_dw2" = "PMC_GPP_D"
+
+ device domain 0 on
+ subsystemid 0x1558 0x866d inherit
+
+ device ref pcie5_0 on
+ # PCIe PEG2 x8, Clock 3 (DGPU)
+ register "cpu_pcie_rp[CPU_RP(2)]" = "{
+ .clk_src = 3,
+ .clk_req = 3,
+ .flags = PCIE_RP_LTR,
+ }"
+ end
+ device ref pcie4_0 on
+ # PCIe PEG0 x4, Clock 0 (SSD2)
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_src = 0,
+ .clk_req = 0,
+ .flags = PCIE_RP_LTR,
+ }"
+ end
+ device ref i2c0 on
+ # Touchpad I2C bus
+ register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ELAN0412""
+ register "generic.desc" = ""ELAN Touchpad""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""FTCS1000""
+ register "generic.desc" = ""FocalTech Touchpad""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 38 on end
+ end
+ end
+ device ref i2c1 off end
+ device ref tbt_pcie_rp0 off end
+ device ref tcss_xhci on
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+ device ref tcss_root_hub on
+ device ref tcss_usb3_port1 on end
+ end
+ end
+ device ref xhci on
+ # USB2
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
+ register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
+ end
+ device ref pcie_rp5 on
+ # PCIe RP#5 x4, Clock 1 (SSD)
+ register "pch_pcie_rp[PCH_RP(5)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_LTR,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ # XXX: Enable tied to 3.3VS?
+ #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+ register "disable_l23" = "true"
+ register "srcclk_pin" = "1" # SSD1_CLKREQ#
+ device generic 0 on end
+ end
+ end
+ device ref pcie_rp9 on
+ # PCIe RP#9 x1, Clock 6 (GLAN)
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .clk_src = 6,
+ .clk_req = 6,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ # XXX: Enable tied to VDD3?
+ #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+ register "srcclk_pin" = "6" # GLAN_CLKREQ#
+ device generic 0 on end
+ end
+ end
+ device ref pcie_rp10 on
+ # PCIe RP#10 x1, Clock 2 (WLAN)
+ register "pch_pcie_rp[PCH_RP(10)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+ register "srcclk_pin" = "2" # WLAN_CLKREQ#
+ device generic 0 on end
+ end
+ end
+ device ref pcie_rp11 on
+ # PCIe RP#11 x1, Clock 5 (CARD)
+ register "pch_pcie_rp[PCH_RP(11)]" = "{
+ .clk_src = 5,
+ .clk_req = 5,
+ .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ # XXX: Enable tied to 3.3VS?
+ #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B7)" # CARD_PWR_EN
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+ register "srcclk_pin" = "5" # CARD_CLKREQ#
+ device generic 0 on end
+ end
+ end
+ end
+end
diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c b/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c
new file mode 100644
index 0000000..5e6cf7d
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3050/romstage.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ const struct mb_cfg board_cfg = {
+ .type = MEM_TYPE_DDR4,
+ };
+ const struct mem_spd spd_info = {
+ .topo = MEM_TOPO_DIMM_MODULE,
+ .smbus = {
+ [0] = { .addr_dimm[0] = 0x50, },
+ [1] = { .addr_dimm[0] = 0x52, },
+ },
+ };
+ const bool half_populated = false;
+
+ // Set primary display to internal graphics
+ mupd->FspmConfig.PrimaryDisplay = 0;
+
+ mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+ mupd->FspmConfig.GpioOverride = 0;
+
+ memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/board_info.txt b/src/mainboard/system76/adl/variants/gaze17-3060-b/board_info.txt
new file mode 100644
index 0000000..6352efb
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/board_info.txt
@@ -0,0 +1,2 @@
+Board name: gaze17-3060-b
+Release year: 2022
diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/data.vbt b/src/mainboard/system76/adl/variants/gaze17-3060-b/data.vbt
new file mode 100644
index 0000000..4fe5dd0
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/data.vbt
Binary files differ
diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c
new file mode 100644
index 0000000..07fa383
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+ /* ------- GPIO Group GPD ------- */
+ PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+ PAD_CFG_GPO(GPD7, 0, DEEP), // GPD_7 (Strap 16)
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+ PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
+
+ /* ------- GPIO Group GPP_A ------- */
+ PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+ PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0
+ PAD_NC(GPP_A6, NONE),
+ PAD_NC(GPP_A7, NONE),
+ PAD_NC(GPP_A8, NONE),
+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
+ PAD_NC(GPP_A11, NONE),
+ PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1
+ PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
+ //PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+ _PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // DP_E_HPD
+ PAD_NC(GPP_A16, NONE), // USB_OC3#
+ PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
+ _PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
+ PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
+ PAD_CFG_GPI(GPP_A20, NONE, PLTRST), // PEG_WAKE#
+ PAD_NC(GPP_A21, NONE),
+ PAD_NC(GPP_A22, NONE),
+ PAD_NC(GPP_A23, NONE),
+
+ /* ------- GPIO Group GPP_B ------- */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+ //PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+ PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+ PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+ PAD_NC(GPP_B5, NONE),
+ PAD_NC(GPP_B6, NONE),
+ PAD_NC(GPP_B7, NONE),
+ PAD_NC(GPP_B8, NONE),
+ //PAD_CFG_GPO(GPP_B9, 0, DEEP),
+ //PAD_CFG_GPO(GPP_B10, 0, DEEP),
+ PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+ _PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED#
+ PAD_NC(GPP_B15, NONE),
+ PAD_NC(GPP_B16, NONE),
+ PAD_NC(GPP_B17, NONE),
+ PAD_CFG_GPO(GPP_B18, 0, DEEP), // Strap 2 of 24
+ //PAD_CFG_GPO(GPP_B19, 0, DEEP),
+ //PAD_CFG_GPO(GPP_B20, 0, DEEP),
+ //PAD_CFG_GPO(GPP_B21, 0, DEEP),
+ //PAD_CFG_GPO(GPP_B22, 0, DEEP),
+ PAD_CFG_GPO(GPP_B23, 0, DEEP), // Strap 8 of 24
+
+ /* ------- GPIO Group GPP_C ------- */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
+ PAD_CFG_GPO(GPP_C2, 1, PLTRST), // SATA_M2_PWR_EN1
+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+ PAD_CFG_GPO(GPP_C5, 0, DEEP), // Strap 4 of 24
+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SML1_CLK
+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SML1_DATA
+ //PAD_NC(GPP_C8, NONE),
+ //PAD_NC(GPP_C9, NONE),
+ //PAD_NC(GPP_C10, NONE),
+ //PAD_NC(GPP_C11, NONE),
+ //PAD_NC(GPP_C12, NONE),
+ //PAD_NC(GPP_C13, NONE),
+ //PAD_NC(GPP_C14, NONE),
+ //PAD_NC(GPP_C15, NONE),
+ //PAD_NC(GPP_C16, NONE),
+ //PAD_NC(GPP_C17, NONE),
+ //PAD_NC(GPP_C18, NONE),
+ //PAD_NC(GPP_C19, NONE),
+ //PAD_NC(GPP_C20, NONE),
+ //PAD_NC(GPP_C21, NONE),
+ //PAD_NC(GPP_C22, NONE),
+ //PAD_NC(GPP_C23, NONE),
+
+ /* ------- GPIO Group GPP_D ------- */
+ PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+ PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+ PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+ PAD_NC(GPP_D3, NONE),
+ PAD_CFG_GPI(GPP_D4, NONE, DEEP), // PS8461_SW
+ //PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // PEX4_SSD_CLKREQ#
+ //PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD_CLKREQ#
+ //PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+ //PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // PEQ_CLKREQ#
+ PAD_NC(GPP_D9, NONE),
+ PAD_CFG_GPO(GPP_D10, 0, DEEP), // Strap 6 of 24
+ PAD_NC(GPP_D11, NONE),
+ PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // Strap 7 of 24
+ PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+ PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SATA_M2_PWR_EN2
+ PAD_NC(GPP_D15, NONE),
+ PAD_NC(GPP_D16, NONE),
+ PAD_NC(GPP_D17, NONE),
+ PAD_NC(GPP_D18, NONE),
+ PAD_NC(GPP_D19, NONE),
+
+ /* ------- GPIO Group GPP_E ------- */
+ PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+ //_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
+ PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
+ PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
+ PAD_NC(GPP_E5, NONE),
+ PAD_CFG_GPO(GPP_E6, 0, DEEP), // Strap 12 of 24
+ PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+ PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+ PAD_NC(GPP_E10, NONE),
+ PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
+ PAD_CFG_GPO(GPP_E12, 0, DEEP), // TP_ATTN#
+ PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // PCH_EDP_HPD
+ PAD_NC(GPP_E15, NONE),
+ PAD_NC(GPP_E16, NONE),
+ PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3
+ PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD
+ PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD
+ PAD_NC(GPP_E20, NONE),
+ PAD_CFG_GPO(GPP_E21, 0, DEEP), // Strap 14 of 24
+ PAD_NC(GPP_E22, NONE),
+ PAD_NC(GPP_E23, NONE),
+
+ /* ------- GPIO Group GPP_F ------- */
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+ PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST#
+ //PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // XTAL_CLKREQ
+ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+ PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
+ //PAD_CFG_GPO(GPP_F8, 0, DEEP),
+ PAD_NC(GPP_F9, NONE),
+ PAD_CFG_GPO(GPP_F10, 1, DEEP), // CARD_RTD3_RST#
+ PAD_NC(GPP_F11, NONE),
+ PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN
+ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
+ PAD_NC(GPP_F14, NONE),
+ PAD_NC(GPP_F15, NONE),
+ PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
+ PAD_NC(GPP_F17, NONE),
+ PAD_NC(GPP_F18, NONE),
+ //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // LAN_CLKREQ#
+ PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_CPU_SSD1_RST#
+ PAD_NC(GPP_F21, NONE),
+ PAD_NC(GPP_F22, NONE),
+ PAD_NC(GPP_F23, NONE),
+
+ /* ------- GPIO Group GPP_H ------- */
+ PAD_CFG_GPO(GPP_H0, 1, DEEP), // M2_PCH_SSD_RST#
+ PAD_CFG_GPO(GPP_H1, 0, DEEP), // Strap 22 of 24
+ PAD_CFG_GPO(GPP_H2, 1, DEEP), // M2_WLAN_RST#
+ PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
+ PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
+ PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
+ PAD_CFG_GPI(GPP_H10, NONE, DEEP), // UART0_RXD
+ PAD_CFG_GPI(GPP_H11, NONE, DEEP), // UART0_TXD
+ PAD_NC(GPP_H12, NONE),
+ PAD_CFG_GPI(GPP_H13, NONE, DEEP), // DEVSLP1
+ //PAD_NC(GPP_H14, NONE),
+ PAD_NC(GPP_H15, NONE),
+ //PAD_NC(GPP_H16, NONE),
+ PAD_NC(GPP_H17, NONE),
+ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+ PAD_NC(GPP_H19, NONE),
+ PAD_CFG_GPI(GPP_H20, NONE, DEEP), // BL_PWW_EN_EC
+ PAD_CFG_GPI(GPP_H21, NONE, DEEP), // PLVDD_RST_EC
+ PAD_CFG_GPO(GPP_H22, 0, DEEP), // MUX_CTRL_BIOS
+ //PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
+
+ /* ------- GPIO Group GPP_R ------- */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+ PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+ PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+ PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
+ PAD_NC(GPP_R5, NONE),
+ PAD_CFG_GPO(GPP_R6, 0, DEEP), // DMIC_CLK1
+ PAD_CFG_GPO(GPP_R7, 0, DEEP), // DMIC_DATA1
+
+ /* ------- GPIO Group GPP_S ------- */
+ PAD_NC(GPP_S0, NONE),
+ PAD_NC(GPP_S1, NONE),
+ PAD_NC(GPP_S2, NONE),
+ PAD_NC(GPP_S3, NONE),
+ PAD_NC(GPP_S4, NONE),
+ PAD_NC(GPP_S5, NONE),
+ PAD_NC(GPP_S6, NONE),
+ PAD_NC(GPP_S7, NONE),
+
+ /* ------- GPIO Group GPP_T ------- */
+ PAD_NC(GPP_T2, NONE),
+ PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c
new file mode 100644
index 0000000..c2009a8
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/gpio_early.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+ PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
+ PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
+};
+
+void mainboard_configure_early_gpios(void)
+{
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c
new file mode 100644
index 0000000..f28070c
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* Realtek, ALC256 */
+ 0x10ec0256, /* Vendor ID */
+ 0x1558867c, /* Subsystem ID */
+ 12, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x1558867c),
+ AZALIA_RESET(1),
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+ AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb
new file mode 100644
index 0000000..a489bf2
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb
@@ -0,0 +1,155 @@
+chip soc/intel/alderlake
+ # FIVR configuration
+ # Read EXT_RAIL_CONFIG to determine bitmaps
+ # sudo devmem2 0xfe0011b8
+ # 0x0
+ # Read EXT_V1P05_VR_CONFIG
+ # sudo devmem2 0xfe0011c0
+ # 0x1a42000
+ # Read EXT_VNN_VR_CONFIG0
+ # sudo devmem2 0xfe0011c4
+ # 0x1a42000
+ # TODO: v1p05 voltage and vnn icc max?
+ register "ext_fivr_settings" = "{
+ .configure_ext_fivr = 1,
+ .v1p05_enable_bitmap = 0,
+ .vnn_enable_bitmap = 0,
+ .v1p05_supported_voltage_bitmap = 0,
+ .vnn_supported_voltage_bitmap = 0,
+ .v1p05_icc_max_ma = 500,
+ .vnn_sx_voltage_mv = 1050,
+ }"
+
+ # Thermal
+ register "tcc_offset" = "10"
+
+ # GPE configuration
+ register "pmc_gpe0_dw0" = "PMC_GPP_R"
+ register "pmc_gpe0_dw1" = "PMC_GPP_B"
+ register "pmc_gpe0_dw2" = "PMC_GPP_D"
+
+ device domain 0 on
+ subsystemid 0x1558 0x867c inherit
+
+ device ref pcie5_0 on
+ # PCIe PEG2 x8, Clock 3 (DGPU)
+ register "cpu_pcie_rp[CPU_RP(2)]" = "{
+ .clk_src = 3,
+ .clk_req = 3,
+ .flags = PCIE_RP_LTR,
+ }"
+ end
+ device ref igpu on
+ # DDIA is eDP
+ register "ddi_portA_config" = "1"
+ register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
+
+ register "gfx" = "GMA_DEFAULT_PANEL(0)"
+ end
+ device ref pcie4_0 on
+ # PCIe PEG0 x4, Clock 0 (SSD2)
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_src = 0,
+ .clk_req = 0,
+ .flags = PCIE_RP_LTR,
+ }"
+ end
+ device ref i2c0 on
+ # Touchpad I2C bus
+ register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ELAN0412""
+ register "generic.desc" = ""ELAN Touchpad""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""FTCS1000""
+ register "generic.desc" = ""FocalTech Touchpad""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 38 on end
+ end
+ end
+ device ref i2c1 off end
+ device ref tcss_xhci on
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+ device ref tcss_root_hub on
+ device ref tcss_usb3_port1 on end
+ end
+ end
+ device ref tcss_dma0 on end
+ device ref xhci on
+ # USB2
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+ register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
+ end
+ device ref pcie_rp5 on
+ # PCIe root port #5 x1, Clock 2 (WLAN)
+ register "pch_pcie_rp[PCH_RP(5)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_LTR,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+ register "srcclk_pin" = "2" # WLAN_CLKREQ#
+ device generic 0 on end
+ end
+ end
+ device ref pcie_rp6 on
+ # PCIe root port #6 x1, Clock 5 (CARD)
+ register "pch_pcie_rp[PCH_RP(6)]" = "{
+ .clk_src = 5,
+ .clk_req = 5,
+ .flags = PCIE_RP_LTR,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ # XXX: No enable_gpio = no D3cold?
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+ register "srcclk_pin" = "5" # CARD_CLKREQ#
+ device generic 0 on end
+ end
+ end
+ device ref pcie_rp7 on
+ # PCIe root port #7 x1, Clock 6 (GLAN)
+ # Clock source is shared with LAN and hence marked as free running.
+ register "pch_pcie_rp[PCH_RP(7)]" = "{
+ .clk_src = 6,
+ .clk_req = 6,
+ .flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
+ end
+ device ref pcie_rp9 on
+ # PCIe root port #9 x4, Clock 1 (SSD1)
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_LTR,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ # XXX: Enable tied to 3.3VS?
+ #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+ register "disable_l23" = "true" # Fixes suspend on WD drives
+ register "srcclk_pin" = "1" # SSD_CLKREQ#
+ device generic 0 on end
+ end
+ end
+ device ref gbe on end
+ end
+end
diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c
new file mode 100644
index 0000000..5e6cf7d
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/romstage.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ const struct mb_cfg board_cfg = {
+ .type = MEM_TYPE_DDR4,
+ };
+ const struct mem_spd spd_info = {
+ .topo = MEM_TOPO_DIMM_MODULE,
+ .smbus = {
+ [0] = { .addr_dimm[0] = 0x50, },
+ [1] = { .addr_dimm[0] = 0x52, },
+ },
+ };
+ const bool half_populated = false;
+
+ // Set primary display to internal graphics
+ mupd->FspmConfig.PrimaryDisplay = 0;
+
+ mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+ mupd->FspmConfig.GpioOverride = 0;
+
+ memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}