tree cfd2967323c423c1894ad821d12590008250308e
parent c2e796290aa32cb22677cadf467209767cc03f93
author Varun Joshi <varun.joshi@intel.corp-partner.google.com> 1584995076 -0700
committer Furquan Shaikh <furquan@google.com> 1586483847 +0000

soc/intel/tigerlake: Add support to initialize DDR4 Memory

Support to configure DDR4 memory variant.
	-Add support to read SPD data based on different memory topology.
	-Initialize FSP UPD's for DQ and DQS mapping.

BUG=b:151702387

Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I47a5dcad3ee316871a6103b9d53ef7f6fc88d7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39847
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>