arch/x86: consolidate HPET base address definitions
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index 2655298..4e2b8df 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -18,6 +18,7 @@
#include <acpi/acpi.h>
#include <acpi/acpi_ivrs.h>
#include <acpi/acpigen.h>
+#include <arch/hpet.h>
#include <arch/mmio.h>
#include <device/pci.h>
#include <cbmem.h>
@@ -848,10 +849,10 @@
addr->space_id = ACPI_ADDRESS_SPACE_MEMORY;
addr->bit_width = 64;
addr->bit_offset = 0;
- addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff;
- addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
+ addr->addrl = HPET_BASE_ADDRESS & 0xffffffff;
+ addr->addrh = ((unsigned long long)HPET_BASE_ADDRESS) >> 32;
- hpet->id = read32p(CONFIG_HPET_ADDRESS);
+ hpet->id = read32p(HPET_BASE_ADDRESS);
hpet->number = 0;
hpet->min_tick = CONFIG_HPET_MIN_TICKS;
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index f09840d..4052b2e 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -191,10 +191,6 @@
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
depends on HAVE_CMOS_DEFAULT
-config HPET_ADDRESS
- hex
- default 0xfed00000
-
config HPET_MIN_TICKS
hex
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
index ddac440..374ff9d 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
@@ -1,4 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/hpet.h>
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
@@ -89,7 +91,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c
index d1173b5..073e799 100644
--- a/src/mainboard/google/butterfly/early_init.c
+++ b/src/mainboard/google/butterfly/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <stdint.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
@@ -82,7 +83,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c
index 265b13a..d3209d0 100644
--- a/src/mainboard/google/link/early_init.c
+++ b/src/mainboard/google/link/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <stdint.h>
#include <string.h>
#include <device/pci_ops.h>
@@ -91,7 +92,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c
index 8161697..f4769a1 100644
--- a/src/mainboard/google/parrot/early_init.c
+++ b/src/mainboard/google/parrot/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <stdint.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
@@ -60,7 +61,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c
index 920c420..b33f57c2 100644
--- a/src/mainboard/google/stout/early_init.c
+++ b/src/mainboard/google/stout/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <stdint.h>
#include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
@@ -97,7 +98,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index ada0a5c..0232486 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <stdint.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#if CONFIG(USE_NATIVE_RAMINIT)
@@ -21,7 +22,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c
index 54baafb..11b3121 100644
--- a/src/mainboard/intel/emeraldlake2/early_init.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <bootblock_common.h>
#include <stdint.h>
#include <arch/io.h>
@@ -58,7 +59,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c
index 8305648..521695b 100644
--- a/src/mainboard/kontron/ktqm77/early_init.c
+++ b/src/mainboard/kontron/ktqm77/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <bootblock_common.h>
#include <stdint.h>
#include <device/pnp_def.h>
@@ -63,7 +64,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c
index edb5324..7a9163d 100644
--- a/src/mainboard/lenovo/x220/early_init.c
+++ b/src/mainboard/lenovo/x220/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <stdint.h>
#include <acpi/acpi.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
@@ -19,7 +20,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c
index 3d5b3ba..9386620 100644
--- a/src/mainboard/roda/rv11/variants/rv11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <stdint.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
@@ -17,7 +18,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c
index d36c8f9..b3378ba 100644
--- a/src/mainboard/roda/rv11/variants/rw11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <bootblock_common.h>
#include <stdint.h>
#include <device/pnp_ops.h>
@@ -47,7 +48,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c
index a885f5b..26c8826 100644
--- a/src/mainboard/samsung/lumpy/early_init.c
+++ b/src/mainboard/samsung/lumpy/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
@@ -123,7 +124,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c
index dbfc2d2..dfb1f4d0 100644
--- a/src/mainboard/samsung/stumpy/early_init.c
+++ b/src/mainboard/samsung/stumpy/early_init.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <bootblock_common.h>
#include <stdint.h>
#include <pc80/mc146818rtc.h>
@@ -108,7 +109,7 @@
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index fedb683..e1a9337 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <console/console.h>
#include <console/usb.h>
#include <string.h>
@@ -351,7 +352,7 @@
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
- .hpet_address = CONFIG_HPET_ADDRESS,
+ .hpet_address = HPET_BASE_ADDRESS,
.rcba = CONFIG_FIXED_RCBA_MMIO_BASE,
.pmbase = DEFAULT_PMBASE,
.gpiobase = DEFAULT_GPIOBASE,
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index cc820cd..c52203a 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <console/console.h>
#include <console/usb.h>
#include <cf9_reset.h>
@@ -235,7 +236,7 @@
pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE;
pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE;
pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
- pei_data->hpet_address = CONFIG_HPET_ADDRESS;
+ pei_data->hpet_address = HPET_BASE_ADDRESS;
pei_data->thermalbase = 0xfed08000;
pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE);
pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index a6efce7..fc04b25 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -15,11 +15,6 @@
#define GNB_IO_APIC_ADDR 0xfec01000
#define SPI_BASE_ADDRESS 0xfec10000
-#include <arch/hpet.h> /* This will be removed in a follow-up patch */
-#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
-#error HPET address must be 0xfed00000
-#endif
-
/* FCH AL2AHB Registers */
#define ALINK_AHB_ADDRESS 0xfedc0000
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 1ce581e..853008b 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -10,11 +10,6 @@
#define GNB_IO_APIC_ADDR 0xfec01000
#define SPI_BASE_ADDRESS 0xfec10000
-#include <arch/hpet.h> /* This will be removed in a follow-up patch */
-#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
-#error HPET address must be 0xfed00000
-#endif
-
/* FCH AL2AHB Registers */
#define ALINK_AHB_ADDRESS 0xfedc0000
#define AL2AHB_CONTROL_CLK_OFFSET 0x10
diff --git a/src/soc/amd/sabrina/include/soc/iomap.h b/src/soc/amd/sabrina/include/soc/iomap.h
index cfe4184..7f9746b 100644
--- a/src/soc/amd/sabrina/include/soc/iomap.h
+++ b/src/soc/amd/sabrina/include/soc/iomap.h
@@ -15,11 +15,6 @@
#define GNB_IO_APIC_ADDR 0xfec01000
#define SPI_BASE_ADDRESS 0xfec10000
-#include <arch/hpet.h> /* This will be removed in a follow-up patch */
-#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
-#error HPET address must be 0xfed00000
-#endif
-
/* FCH AL2AHB Registers */
#define ALINK_AHB_ADDRESS 0xfedc0000
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 75c0973..76e6e77 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -16,11 +16,6 @@
#define APU_I2C2_BASE 0xfedc4000
#define APU_I2C3_BASE 0xfedc5000
-#include <arch/hpet.h> /* This will be removed in a follow-up patch */
-#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
-#error HPET address must be 0xfed00000
-#endif
-
#define APU_UART0_BASE 0xfedc6000
#define APU_UART1_BASE 0xfedc8000
diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl
index c76cf22..5933070 100644
--- a/src/soc/intel/baytrail/acpi/lpc.asl
+++ b/src/soc/intel/baytrail/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
/* Intel LPC Bus Device - 0:1f.0 */
Device (LPCB)
@@ -44,7 +46,7 @@
Name(_CRS, ResourceTemplate()
{
- Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400)
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400)
})
}
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
index 0a22162..76af8fd 100644
--- a/src/soc/intel/braswell/acpi/lpc.asl
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
/* Intel LPC Bus Device - 0:1f.0 */
Device (LPCB)
@@ -55,7 +57,7 @@
Name(_CRS, ResourceTemplate()
{
- Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400)
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400)
})
}
#endif
diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl
index e37c6d0..b6b77c8 100644
--- a/src/soc/intel/broadwell/pch/acpi/lpc.asl
+++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
@@ -64,7 +66,7 @@
Name (BUF0, ResourceTemplate ()
{
- Memory32Fixed (ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
+ Memory32Fixed (ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -77,15 +79,15 @@
If (HPTE) {
CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (HPAS == 1) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x1000
+ HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (HPAS == 2) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x2000
+ HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (HPAS == 3) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x3000
+ HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}
diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl
index 2e86157..98e979e 100644
--- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
@@ -78,7 +80,7 @@
Name(BUF0, ResourceTemplate()
{
- Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -91,15 +93,15 @@
If (HPTE) {
CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (Lequal(HPAS, 1)) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x1000
+ HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (Lequal(HPAS, 2)) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x2000
+ HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (Lequal(HPAS, 3)) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x3000
+ HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 972ca76..238661c 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
#include <arch/io.h>
#include <arch/ioapic.h>
#include <console/console.h>
@@ -213,7 +214,7 @@
u32 reg32, hpet, val;
/* Set HPET base address and enable it */
- printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS);
+ printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_BASE_ADDRESS);
reg32 = pci_read_config32(dev, GEN_CNTL);
/*
* Bit 17 is HPET enable bit.
@@ -221,7 +222,7 @@
*/
reg32 &= ~(3 << 15); /* Clear it */
- hpet = CONFIG_HPET_ADDRESS >> 12;
+ hpet = HPET_BASE_ADDRESS >> 12;
hpet &= 0x3;
reg32 |= (hpet << 15);
@@ -234,7 +235,7 @@
val &= 0x7;
if ((val & 0x4) && (hpet == (val & 0x3))) {
- printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS);
+ printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_BASE_ADDRESS);
} else {
printk(BIOS_WARNING, "HPET was not enabled correctly\n");
reg32 &= ~(1 << 17); /* Clear Enable */
diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl
index 72e28eb..d2e8890 100644
--- a/src/southbridge/intel/i82801gx/acpi/lpc.asl
+++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
@@ -60,7 +62,7 @@
Name(BUF0, ResourceTemplate()
{
- Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -73,15 +75,15 @@
If (HPTE) {
CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (HPAS == 1) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x1000
+ HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (HPAS == 2) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x2000
+ HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (HPAS == 3) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x3000
+ HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}
diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl
index b97b010..9227735 100644
--- a/src/southbridge/intel/i82801ix/acpi/lpc.asl
+++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
@@ -60,7 +62,7 @@
Name(BUF0, ResourceTemplate()
{
- Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -73,15 +75,15 @@
If (HPTE) {
CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (Lequal(HPAS, 1)) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x1000
+ HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (Lequal(HPAS, 2)) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x2000
+ HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (Lequal(HPAS, 3)) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x3000
+ HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}
diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl
index b97b010..9227735 100644
--- a/src/southbridge/intel/i82801jx/acpi/lpc.asl
+++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
@@ -60,7 +62,7 @@
Name(BUF0, ResourceTemplate()
{
- Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -73,15 +75,15 @@
If (HPTE) {
CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (Lequal(HPAS, 1)) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x1000
+ HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (Lequal(HPAS, 2)) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x2000
+ HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (Lequal(HPAS, 3)) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x3000
+ HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
index 51d777e..1e02467 100644
--- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
// Intel LPC Bus Device - 0:1f.0
#include <southbridge/intel/lynxpoint/pch.h>
@@ -66,7 +68,7 @@
Name (BUF0, ResourceTemplate ()
{
- Memory32Fixed (ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
+ Memory32Fixed (ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -79,15 +81,15 @@
If (HPTE) {
CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (HPAS == 1) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x1000
+ HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (HPAS == 2) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x2000
+ HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (HPAS == 3) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x3000
+ HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}