soc/intel/xeon_sp: Update FSP-T UPD for FSP2.4
FSP2.4 and previous FSP versions have different FSP-T UPD
parameter settings.
Change-Id: I48384944ac69636cca2acd8169d3dd15f90362ec
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81313
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
index 62ca48f..3e9922f6 100644
--- a/src/soc/intel/xeon_sp/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -14,6 +14,32 @@
#include <soc/iomap.h>
#include <soc/pci_devs.h>
+#if (CONFIG(PLATFORM_USES_FSP2_4))
+const FSPT_UPD temp_ram_init_params = {
+ .FspUpdHeader = {
+ .Signature = FSPT_UPD_SIGNATURE,
+ .Revision = 2,
+ .Reserved = {0},
+ },
+ .FsptArchUpd = {
+ .Revision = 2,
+ .Length = 32,
+ .FspDebugHandler = 0,
+ .Reserved1 = {0},
+ },
+ .FsptCoreUpd = {
+ .MicrocodeRegionBase = 0,
+ .MicrocodeRegionLength = 0,
+ .CodeRegionBase = (UINT64)CACHE_ROM_BASE,
+ .CodeRegionLength = (UINT64)CACHE_ROM_SIZE,
+ },
+ .FsptConfig = {
+ .FsptPort80RouteDisable = 0,
+ .ReservedTempRamInitUpd = {0},
+ },
+ .UpdTerminator = 0x55AA,
+};
+#else
const FSPT_UPD temp_ram_init_params = {
.FspUpdHeader = {
.Signature = FSPT_UPD_SIGNATURE,
@@ -34,6 +60,7 @@
.UnusedUpdSpace0 = {0},
.UpdTerminator = 0x55AA,
};
+#endif //(!CONFIG(PLATFORM_USES_FSP2_4))
static uint64_t assembly_timestamp;
static uint64_t bootblock_timestamp;