diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 58e3ca2..a3481c6 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -387,6 +387,20 @@
 	fast_spi_init();
 }
 
+/* Clear SPI Synchronous SMI status bit and return its value. */
+bool fast_spi_clear_sync_smi_status(void)
+{
+	const uint32_t bios_cntl = pci_read_config32(PCH_DEV_SPI, SPI_BIOS_CONTROL);
+	const bool smi_asserted = bios_cntl & SPI_BIOS_CONTROL_SYNC_SS;
+	/*
+	 * Do not unconditionally write 1 to clear SYNC_SS. Hardware could set
+	 * SYNC_SS here (after we read but before we write SPI_BIOS_CONTROL),
+	 * and the event would be lost when unconditionally clearing SYNC_SS.
+	 */
+	pci_write_config32(PCH_DEV_SPI, SPI_BIOS_CONTROL, bios_cntl);
+	return smi_asserted;
+}
+
 /* Read SPI Write Protect disable status. */
 bool fast_spi_wpd_status(void)
 {