Documentation: gpio: Update table as per coreboot guidelines
This patch fixes the table issue in markdown file introduced with commit
5338a16b (Documentation: gpio: Fix table).
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic4f27f46a9d219098612d8b7747ae26116506fce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md
index 5f30ea7..216ba5d 100644
--- a/Documentation/getting_started/gpio.md
+++ b/Documentation/getting_started/gpio.md
@@ -167,32 +167,61 @@
As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
supports four different types of GPIO reset as:
-| PAD Reset Config | Platform Reset | GPP | GPD |
-|-------------------------------------------------|----------------|-----|-----|
-| 00 - Power Good (GPP: RSMRST, GPD: DSW_PWROK) | Warm Reset | N | N |
-| | Cold Reset | N | N |
-| | S3/S4/S5 | N | N |
-| | Global Reset | N | N |
-| | Deep Sx | Y | N |
-| | G3 | Y | N |
-| 01 - Deep | Warm Reset | Y | Y |
-| | Cold Reset | Y | Y |
-| | S3/S4/S5 | N | N |
-| | Global Reset | Y | Y |
-| | Deep Sx | Y | Y |
-| | G3 | Y | Y |
-| 10 - Host Reset/PLTRST | Warm Reset | Y | Y |
-| | Cold Reset | Y | Y |
-| | S3/S4/S5 | Y | Y |
-| | Global Reset | Y | Y |
-| | Deep Sx | Y | Y |
-| | G3 | Y | Y |
-| 11 - Resume Reset (GPP: Reserved, GPD: RSMRST) | Warm Reset | - | N |
-| | Cold Reset | - | N |
-| | S3/S4/S5 | - | N |
-| | Global Reset | - | N |
-| | Deep Sx | - | Y |
-| | G3 | - | Y |
+```eval_rst
++------------------------+----------------+-------------+-------------+
+| | | PAD Reset ? |
++ PAD Reset Config + Platform Reset +-------------+-------------+
+| | | GPP | GPD |
++========================+================+=============+=============+
+| | 00 - Power Good | Warm Reset | N | N |
+| | (GPP: RSMRST, +----------------+-------------+-------------+
+| | GPD: DSW_PWROK) | Cold Reset | N | N |
+| |----------------+-------------+-------------+
+| | S3/S4/S5 | N | N |
+| +----------------+-------------+-------------+
+| | Global Reset | N | N |
+| +----------------+-------------+-------------+
+| | Deep Sx | Y | N |
+| +----------------+-------------+-------------+
+| | G3 | Y | Y |
++------------------------+----------------+-------------+-------------+
+| 01 - Deep | Warm Reset | Y | Y |
+| +----------------+-------------+-------------+
+| | Cold Reset | Y | Y |
+| +----------------+-------------+-------------+
+| | S3/S4/S5 | N | N |
+| +----------------+-------------+-------------+
+| | Global Reset | Y | Y |
+| +----------------+-------------+-------------+
+| | Deep Sx | Y | Y |
+| +----------------+-------------+-------------+
+| | G3 | Y | Y |
++------------------------+----------------+-------------+-------------+
+| 10 - Host Reset/PLTRST | Warm Reset | Y | Y |
+| +----------------+-------------+-------------+
+| | Cold Reset | Y | Y |
+| +----------------+-------------+-------------+
+| | S3/S4/S5 | Y | Y |
+| +----------------+-------------+-------------+
+| | Global Reset | Y | Y |
+| +----------------+-------------+-------------+
+| | Deep Sx | Y | Y |
+| +----------------+-------------+-------------+
+| | G3 | Y | Y |
++------------------------+----------------+-------------+-------------+
+| | 11 - Resume Reset | Warm Reset | - | N |
+| | (GPP: Reserved, +----------------+-------------+-------------+
+| | GPD: RSMRST) | Cold Reset | - | N |
+| +----------------+-------------+-------------+
+| | S3/S4/S5 | - | N |
+| +----------------+-------------+-------------+
+| | Global Reset | - | N |
+| +----------------+-------------+-------------+
+| | Deep Sx | - | Y |
+| +----------------+-------------+-------------+
+| | G3 | - | Y |
++------------------------+----------------+-------------+-------------+
+```
Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking
specific register fields in the PAD configuration register.