##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc.
##

# -----------------------------------------------------------------
entries

# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96           4       r       0        status_c_rsvd
#100          1       r       0        uf_flag
#101          1       r       0        af_flag
#102          1       r       0        pf_flag
#103          1       r       0        irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104          7       r       0        status_d_rsvd
#111          1       r       0        valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112          8       r       0        diag_rsvd1

# -----------------------------------------------------------------
0          120       r       0        reserved_memory
#120        264       r       0        unused

# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384          1       e       4        boot_option
385          1       e       4        last_boot
388          4       r       0        reboot_bits
#390          2       r       0        unused?

# -----------------------------------------------------------------
# coreboot config options: console
392          3       e       5        baud_rate
395          4       e       6        debug_level
#399          1       r       0        unused

# coreboot config options: cpu
400          1       e       2        hyper_threading
#401          7       r       0        unused

# coreboot config options: southbridge
408          1       e       1        nmi
409          2       e       7        power_on_after_fail
#411          5       r       0        unused

# coreboot config options: bootloader
#Used by ChromeOS:
416        128       r        0        vbnv
#544        440       r       0        unused

# SandyBridge MRC Scrambler Seed values
896         32        r       0        mrc_scrambler_seed
928         32        r       0        mrc_scrambler_seed_s3

# coreboot config options: check sums
984         16       h       0        check_sum
#1000        24       r       0        amd_reserved

# -----------------------------------------------------------------

enumerations

#ID value   text
1     0     Disable
1     1     Enable
2     0     Enable
2     1     Disable
4     0     Fallback
4     1     Normal
5     0     115200
5     1     57600
5     2     38400
5     3     19200
5     4     9600
5     5     4800
5     6     2400
5     7     1200
6     1     Emergency
6     2     Alert
6     3     Critical
6     4     Error
6     5     Warning
6     6     Notice
6     7     Info
6     8     Debug
6     9     Spew
7     0     Disable
7     1     Enable
7     2     Keep
8     0     AHCI
8     1     Compatible
# -----------------------------------------------------------------
checksums

checksum 392 415 984