##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
if BOARD_INTEL_D945GCLF

config BOARD_SPECIFIC_OPTIONS # dummy
	def_bool y
	select CPU_INTEL_SOCKET_441
	select NORTHBRIDGE_INTEL_I945
	select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
	select CHECK_SLFRCS_ON_RESUME
	select SOUTHBRIDGE_INTEL_I82801GX
	select SUPERIO_SMSC_LPC47M15X
	select HAVE_OPTION_TABLE
	select HAVE_PIRQ_TABLE
	select HAVE_MP_TABLE
	select HAVE_ACPI_TABLES
	select HAVE_ACPI_RESUME
	select BOARD_ROMSIZE_KB_512
	select CHANNEL_XOR_RANDOMIZATION

config MAINBOARD_DIR
	string
	default intel/d945gclf

config MAINBOARD_PART_NUMBER
	string
	default "D945GCLF"

config MMCONF_BASE_ADDRESS
	hex
	default 0xf0000000

config IRQ_SLOT_COUNT
	int
	default 18

config MAX_CPUS
	int
	default 4

endif # BOARD_INTEL_D945GCLF