##
## This file is part of the coreboot project.
##
## Copyright (C) 2009-2010 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

config ARCH_X86
	bool
	default n
	select PCI

# stage selectors for x86

config ARCH_BOOTBLOCK_X86_32
	bool
	default n
	select ARCH_X86
	select BOOTBLOCK_CUSTOM

config ARCH_VERSTAGE_X86_32
	bool
	default n

config ARCH_ROMSTAGE_X86_32
	bool
	default n

config ARCH_RAMSTAGE_X86_32
	bool
	default n

# stage selectors for x64

config ARCH_BOOTBLOCK_X86_64
	bool
	default n
	select ARCH_X86
	select BOOTBLOCK_CUSTOM

config ARCH_VERSTAGE_X86_64
	bool
	default n

config ARCH_ROMSTAGE_X86_64
	bool
	default n

config ARCH_RAMSTAGE_X86_64
	bool
	default n

# This is an SMP option. It relates to starting up APs.
# It is usually set in mainboard/*/Kconfig.
# TODO: Improve description.
config AP_IN_SIPI_WAIT
	bool
	default n
	depends on ARCH_X86 && SMP

# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
# can boot AP CPUs to enable their shared caches.
config SIPI_VECTOR_IN_ROM
	bool
	default n
	depends on ARCH_X86

config RAMBASE
	hex
	default 0x100000

# This is something you almost certainly don't want to mess with.
# How many SIPIs do we send when starting up APs and cores?
# The answer in 2000 or so was '2'. Nowadays, on many systems,
# it is 1. Set a safe default here, and you can override it
# on reasonable platforms.
config NUM_IPI_STARTS
	int
	default 2

config ROMCC
	bool
	default n

config LATE_CBMEM_INIT
	def_bool n
	help
	  Enable this in chipset's Kconfig if northbridge does not implement
	  early get_top_of_ram() call for romstage. CBMEM tables will be
	  allocated late in ramstage, after PCI devices resources are known.

config PC80_SYSTEM
	bool
	default y if ARCH_X86

config BOOTBLOCK_MAINBOARD_INIT
	string

config BOOTBLOCK_NORTHBRIDGE_INIT
	string

config BOOTBLOCK_RESETS
	string

config HAVE_CMOS_DEFAULT
	def_bool n

config CMOS_DEFAULT_FILE
	string
	default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
	depends on HAVE_CMOS_DEFAULT

config BOOTBLOCK_SOUTHBRIDGE_INIT
	string

config IOAPIC_INTERRUPTS_ON_FSB
	bool
	default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS

config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
	bool
	default n

config HPET_ADDRESS
	hex
	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE

config ID_SECTION_OFFSET
	hex
	default 0x80

config COMPILE_IN_DSDT
	bool "compile in DSDT and use that over DSDT in CBFS"
	default n