commit | 4de2c342fbfe2d96afe1f4d6ccd9be22367aacad | [log] [tgz] |
---|---|---|
author | Subrata Banik <subratabanik@google.com> | Fri Feb 11 13:58:31 2022 +0530 |
committer | Felix Held <felix-coreboot@felixheld.de> | Sat Feb 26 00:15:28 2022 +0000 |
tree | 2d4b5cab8ef5f0259d5d32ee51cec6b970f02f99 | |
parent | 737ad67d122b24f8309ad76b66b5d7a26873eb39 [diff] |
soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq This fixes no practical problem, especially for coreboot where only one process should access the SPI controller. It makes the code look more spec compliant. As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. Software must initiate the next SPI transaction when this bit is 0. Add non-blocking mechanism with `5sec` timeout to report back error if current SPI transaction is failing due to on-going SPI access. BUG=b:215255210 TEST=Able to boot brya and verified SPI read/write is successful. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.