tree e0b766fb7c4b1e22947faf0086a67218a92f0ef8
parent 3a873b5c9a70ec41488161b491ffe5ac94bb554e
author Sridhar Siricilla <sridhar.siricilla@intel.com> 1604904202 +0530
committer Subrata Banik <subrata.banik@intel.com> 1606660746 +0000

soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration

TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47436
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>