Intel Firmware Support Package (FSP)-specific documentation

This section contains documentation about Intel-FSP in public domain.


As Intel doesn't even list known bugs, they are collected here until those are fixed. If possible a workaround is described here as well.


  • IA32_FEATURE_CONTROL MSR is locked in FSP-M

    • Release MR2
    • Writing the MSR is required in ramstage for Intel TXT
    • Workaround: none
    • Issue on public tracker: Issue 10
  • FSP-S asserts if the thermal PCI device 00:1f.6 is disabled

    • Release MR2
    • FSP expects the PCI device to be enabled
    • FSP expects BARs to be properly assigned
    • Workaround: Don't disable this PCI device
    • Issue on public tracker: Issue 13
  • FSP Notify(EnumInitPhaseAfterPciEnumeration) hangs if 00:02.03/00:02.03 are hidden

    • Release MR2
    • Seems to get stuck on some SKUs only if hidden after MemoryInit
    • Workaround: Hide before MemoryInit
    • Issue on public tracker: Issue 35


  • MfgId and ModulePartNum in the DIMM_INFO struct are empty

    • Release 3.7.1
    • Those values are typically consumed by SMBIOS type 17
    • Workaround: none
    • Issue on public tracker: Issue 22
  • MRC forces memory re-training on cold boot on boards with Intel SPS

    • Releases 3.7.1, 3.7.6
    • Workaround: Flash Intel ME instead of SPS
    • Issue on public tracker: Issue 41


  • Internal UART can't be disabled using PcdEnableHsuart*
    • Release MR2
    • Workaround: Disable internal UART manually after calling FSP
    • Issue on public tracker: Issue 10

Open Source Intel FSP specification

Additional Features in FSP 2.1 specification

Official bugtracker