diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 7e0cc20..42a2a74 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -285,13 +285,6 @@
 	writel_(ichspi_bbar, cntlr.bbar);
 }
 
-int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)
-{
-	slave->bus = bus;
-	slave->cs = cs;
-	return 0;
-}
-
 void spi_init(void)
 {
 	uint8_t *rcrb; /* Root Complex Register Block */
@@ -348,17 +341,6 @@
 
 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
 
-int spi_claim_bus(const struct spi_slave *slave)
-{
-	/* Handled by ICH automatically. */
-	return 0;
-}
-
-void spi_release_bus(const struct spi_slave *slave)
-{
-	/* Handled by ICH automatically. */
-}
-
 typedef struct spi_transaction {
 	const uint8_t *out;
 	uint32_t bytesout;
@@ -527,7 +509,7 @@
 	return min(cntlr.databytes, buf_len);
 }
 
-int spi_xfer(const struct spi_slave *slave, const void *dout,
+static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 		size_t bytesout, void *din, size_t bytesin)
 {
 	uint16_t control;
@@ -675,6 +657,18 @@
 	return 0;
 }
 
+static const struct spi_ctrlr spi_ctrlr = {
+	.xfer = spi_ctrlr_xfer,
+};
+
+int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)
+{
+	slave->bus = bus;
+	slave->cs = cs;
+	slave->ctrlr = &spi_ctrlr;
+	return 0;
+}
+
 /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
 static void ich_hwseq_set_addr(uint32_t addr)
 {