commit | 126162c38f47cab8569cae70373d5b512e071c14 | [log] [tgz] |
---|---|---|
author | David Wu <david_wu@quanta.corp-partner.google.com> | Fri Jul 23 11:36:33 2021 +0800 |
committer | Felix Held <felix-coreboot@felixheld.de> | Mon Oct 04 18:41:03 2021 +0000 |
tree | 7cfa4ebcb040d250cfd3132d2ce1e3846204d867 | |
parent | 4a48dbe60bb39b2114f1a4c9bfc02a8d1a8e258f [diff] |
mb/google/brya: Enable DDR4 SODIMM for brask Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in brask device tree and add SPD addressese for the two DIMMs. Separate the Kconfig items of brya and brask. Move HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya and add config SPD_CACHE_IN_FMAP to brask. Add a new section RW_SPD_CACHE to fmd for caching SPD data. The renamed romstage.c is used by both brya and brask and a new function variant_get_spd_info is provided to support the different SPD source types. BUG=b:194055762 BRANCH=None TEST=build pass Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.