soc/intel/meteorlake: Add `.final` to check FSP reset pending request
This patch adds an API to check FSP reset pending requests. This
information is useful to understand if FSP would like boot firmware to
issue any reset to complete the silicon initialization.
As per recent debug it has been found that, FSP is accumulating all
platform resets and executing a single reset from FSP Notify Phase.
As coreboot skipped calling into the FSP Notify APIs hence, it might
have missed the scope to issue the platform reset.
BUG=b:282266168
TEST=Able to build and boot google/rex and able to detect FSP reset
pending request.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf7c996f09affa099c9124773fe2d581f370d1a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c
index 036c126d..d249dd4 100644
--- a/src/soc/intel/meteorlake/chip.c
+++ b/src/soc/intel/meteorlake/chip.c
@@ -15,6 +15,7 @@
#include <intelblocks/systemagent.h>
#include <intelblocks/tcss.h>
#include <intelblocks/xdci.h>
+#include <soc/intel/common/reset.h>
#include <soc/intel/common/vbt.h>
#include <soc/iomap.h>
#include <soc/itss.h>
@@ -226,8 +227,24 @@
block_gpio_enable(dev);
}
+static void soc_init_final_device(void *chip_info)
+{
+ uint32_t reset_status = fsp_get_pch_reset_status();
+
+ if (reset_status == FSP_SUCCESS)
+ return;
+
+ /* Handle any pending reset request from previously executed FSP APIs */
+ fsp_handle_reset(reset_status);
+
+ /* Control shouldn't return here */
+ die_with_post_code(POST_HW_INIT_FAILURE,
+ "Failed to handle the FSP reset request with error 0x%08x\n", reset_status);
+}
+
struct chip_operations soc_intel_meteorlake_ops = {
CHIP_NAME("Intel Meteorlake")
.enable_dev = &soc_enable,
.init = &soc_init_pre_device,
+ .final = &soc_init_final_device,
};