diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index b1c4c78..3960724 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -187,4 +187,12 @@
 	help
 	  Enable Rank Margining Tool. This option is intended for debugging and
 	  validation and should normally be disabled.
+
+config RMT_MEM_POR_FREQ
+	bool "Enforce Plan Of Record restrictions for DDR5 frequency and voltage"
+	default n
+	depends on ENABLE_RMT
+	help
+	  When RMT is enabled. Select this option to enforce Intel Plan Of Record(POR)
+	  restriction on DDR5 frequency & voltage settings.
 endif
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index 2b377a4..4cce21f 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -279,7 +279,8 @@
 		mupd->FspmConfig.serialDebugMsgLvl = 0x3;
 		mupd->FspmConfig.AllowedSocketsInParallel = 0x1;
 		mupd->FspmConfig.EnforcePopulationPor = 0x1;
-		mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0;
+		if (CONFIG(RMT_MEM_POR_FREQ))
+			mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0;
 	}
 
 	/* SPR-FSP has no UPD to disable HDA, so do it manually here... */