sb/intel/lynxpoint: Do not mask out TCO status bits
Not all TCO status bits have a corresponding enable bit. Masking out the
status register with the enable register causes these events to be lost.
Tested on Asrock B85M Pro4, BIOSWR_STS events are now detected.
Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 7b84689..8117b4d 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -298,12 +298,11 @@
* TCO
*/
-/* Clear TCO status and return events that are enabled and active */
+/* Clear TCO status and return events that are active */
static u32 reset_tco_status(void)
{
u32 tcobase = get_pmbase() + 0x60;
u32 tco_sts = inl(tcobase + 0x04);
- u32 tco_en = inl(get_pmbase() + 0x68);
/* Don't clear BOOT_STS before SECOND_TO_STS */
outl(tco_sts & ~(1 << 18), tcobase + 0x04);
@@ -312,7 +311,7 @@
if (tco_sts & (1 << 18))
outl(tco_sts & (1 << 18), tcobase + 0x04);
- return tco_sts & tco_en;
+ return tco_sts;
}
/* Print TCO status bits */