diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h
new file mode 100644
index 0000000..d8b1903
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h
@@ -0,0 +1,92 @@
+/** @file
+  CXL GUID HOB definitions
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 2019 - 2021 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _CXL_NODE_HOB_
+#define _CXL_NODE_HOB_
+
+#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
+
+#ifndef MAX_CXL_HDM_RANGES
+#define MAX_CXL_HDM_RANGES        0x2        // Maximum number of CXL HDM ranges per CXL end device.
+#endif
+
+#ifndef MAX_CXL_PER_SOCKET
+#define MAX_CXL_PER_SOCKET          8
+#endif
+
+#define CXL_NODE_ATTR_MEM           BIT0
+#define CXL_NODE_ATTR_PERSISTENT    BIT1
+#define CXL_NODE_ATTR_MEM_HW_INIT   BIT2
+#define CXL_NODE_ATTR_ACCELERATOR   BIT3
+
+typedef UINT32 CXL_NODE_ATTR;
+
+#pragma pack(1)
+
+//
+// CDAT DSEMTS EFI Memory Type and Attribute
+//
+typedef enum {
+  CxlEfiConventionalMemory        = 0x0,
+  CxlEfiConventionalMemorySp      = 0x1,
+  CxlEfiReservedMemoryType        = 0x2,
+  MaxCxlEfiMemType
+} CXL_EFI_MEM_TYPE;
+
+typedef struct {
+  UINT32              RdLatency;
+  UINT32              WrLatency;
+  UINT32              RdBandwidth;
+  UINT32              WrBandwidth;
+} CXL_PERF_DATA;
+
+typedef struct {
+  UINT64                       SerialNumber;
+  UINT16                       VendorId;
+  CXL_NODE_ATTR                Attr;
+  UINT32                       Address;
+  UINT32                       Size;
+  UINT8                        Ways;
+  UINT8                        SocketBitmap;
+  CXL_EFI_MEM_TYPE             EfiMemType;
+  CXL_PERF_DATA                InitiatorPerfData;        // Performance data between device egress and initiator.
+  CXL_PERF_DATA                TargetPerfData;           // Performance data of entire target memory region.
+  CXL_PERF_DATA                InitiatorTargetPerfData;  // performance data between initiator and the device memory.
+} CXL_NODE_INFO;
+
+typedef struct {
+  UINT8            CxlNodeCount;
+  //
+  // CXL node info for UEFI memory map and ACPI tables construction
+  //
+  CXL_NODE_INFO    CxlNodeInfo[MAX_CXL_PER_SOCKET * MAX_CXL_HDM_RANGES];
+} CXL_NODE_SOCKET;
+
+#pragma pack()
+
+#endif //#ifndef _CXL_NODE_HOB_
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/EnhancedWarningLogLib.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/EnhancedWarningLogLib.h
new file mode 100644
index 0000000..0bbed0b
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/EnhancedWarningLogLib.h
@@ -0,0 +1,167 @@
+/** @file
+  Interface header file for the Enhanced warning log library class.
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _ENHANCED_WARNING_LOG_LIB_
+#define _ENHANCED_WARNING_LOG_LIB_
+
+#define FSP_RESERVED_LEN                 12
+
+#pragma pack(1)
+
+///
+/// Enhanced Warning Log Header
+///
+typedef struct {
+  EFI_GUID  EwlGuid;      /// GUID that uniquely identifies the EWL revision
+  UINT32    Size;         /// Total size in bytes including the header and buffer
+  UINT32    FreeOffset;   /// Offset of the beginning of the free space from byte 0
+                          /// of the buffer immediately following this structure
+                          /// Can be used to determine if buffer has sufficient space for next entry
+  UINT32    Crc;          /// 32-bit CRC generated over the whole size minus this crc field
+                          /// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7])
+                          /// Consumers can ignore CRC check if not needed.
+  UINT32    Reserved;     /// Reserved for future use, must be initialized to 0
+} EWL_HEADER;
+
+///
+/// List of all entry types supported by this revision of EWL
+///
+typedef enum {
+  EwlType0  = 0,
+  EwlType1  = 1,
+  EwlType2  = 2,
+  EwlType3  = 3,
+  EwlType4  = 4,
+  EwlType5  = 5,
+  EwlType6  = 6,
+  EwlType7  = 7,
+  EwlType8  = 8,
+  EwlType9  = 9,
+  EwlType10 = 10,
+  EwlType11 = 11,
+  EwlType12 = 12,
+  EwlType13 = 13,
+  EwlType14 = 14,
+  EwlType15 = 15,
+  EwlType16 = 16,
+  EwlType17 = 17,
+  EwlType18 = 18,
+  EwlType19 = 19,
+  EwlType20 = 20,
+  EwlType21 = 21,
+  EwlType22 = 22,
+  EwlType23 = 23,
+  EwlType24 = 24,
+  EwlType25 = 25,
+  EwlType26 = 26,
+  EwlType27 = 27,
+  EwlType28 = 28,
+  EwlType29 = 29,
+  EwlType30 = 30,
+  EwlType31 = 31,
+  EwlType32 = 32,
+  EwlTypeMax,
+  EwlTypeOem = 0x8000,
+  EwlTypeDelim = MAX_INT32
+} EWL_TYPE;
+
+///
+/// EWL severities
+///
+typedef enum {
+  EwlSeverityInfo,
+  EwlSeverityWarning,
+  EwlSeverityFatal,
+  EwlSeverityMax,
+  EwlSeverityDelim = MAX_INT32
+} EWL_SEVERITY;
+
+
+///
+/// Generic entry header for parsing the log
+///
+typedef struct {
+  EWL_TYPE      Type;
+  UINT16        Size;     /// Entries will be packed by byte in contiguous space
+  EWL_SEVERITY  Severity; /// Warning, error, informational, this may be extended in the future
+} EWL_ENTRY_HEADER;
+
+///
+/// Legacy content provides context of the warning
+///
+typedef struct {
+  UINT8     MajorCheckpoint;  // EWL Spec - Appendix B
+  UINT8     MinorCheckpoint;
+  UINT8     MajorWarningCode; // EWL Spec - Appendix A
+  UINT8     MinorWarningCode;
+} EWL_ENTRY_CONTEXT;
+
+///
+/// Legacy content to specify memory location
+///
+typedef struct {
+  UINT8     Socket;     /// 0xFF = n/a
+  UINT8     Channel;    /// 0xFF = n/a
+  UINT8     PseudoChannel; /// 0xFF = n/a
+  UINT8     Dimm;       /// 0xFF = n/a
+  UINT8     Rank;       /// 0xFF = n/a
+} EWL_ENTRY_MEMORY_LOCATION;
+
+///
+/// Type 3 = Enhanced type for command, control IO errors
+///
+typedef struct {
+  EWL_ENTRY_HEADER           Header;
+  EWL_ENTRY_CONTEXT          Context;
+  EWL_ENTRY_MEMORY_LOCATION  MemoryLocation;
+  UINT8			     reserved1[FSP_RESERVED_LEN]; // MRC_LT Level; MRC_GT Group; GSM_CSN Signal;
+  UINT8                      EyeSize;                     // 0xFF = n/a
+} EWL_ENTRY_TYPE3;
+
+#pragma pack()
+
+///
+/// Enhanced Warning Log Spec defined data log structure
+///
+typedef struct {
+  EWL_HEADER Header;          /// The size will vary by implementation and should not be assumed
+  UINT8      Buffer[4 * 1024];  /// The spec requirement is that the buffer follow the header
+} EWL_PUBLIC_DATA;
+
+///
+/// EWL private data structure.  This is going to be implementation dependent
+///   When we separate OEM hooks via a PPI, we can remove this
+///
+typedef struct {
+  UINT32            bufSizeOverflow;  // Number of bytes that could not be added to buffer
+  UINT32            numEntries;       // Number of entries currently logged
+  EWL_PUBLIC_DATA   status;           // Spec defined EWL
+} EWL_PRIVATE_DATA;
+
+
+#endif // #ifndef _ENHANCED_WARNING_LOG_LIB_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FirmwareVersionInfoHob.h
new file mode 100644
index 0000000..5d09dd2
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FirmwareVersionInfoHob.h
@@ -0,0 +1,59 @@
+/** @file
+  Header file for Firmware Version Information
+ @copyright
+  Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
+#define _FIRMWARE_VERSION_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack(1)
+///
+/// Firmware Version Structure
+///
+typedef struct {
+  UINT8                          MajorVersion;
+  UINT8                          MinorVersion;
+  UINT8                          Revision;
+  UINT16                         BuildNumber;
+} FIRMWARE_VERSION;
+
+///
+/// Firmware Version Information Structure
+///
+typedef struct {
+  UINT8                          ComponentNameIndex;        ///< Offset 0   Index of Component Name
+  UINT8                          VersionStringIndex;        ///< Offset 1   Index of Version String
+  FIRMWARE_VERSION               Version;                   ///< Offset 2-6 Firmware version
+} FIRMWARE_VERSION_INFO;
+
+#ifndef __SMBIOS_STANDARD_H__
+///
+/// The Smbios structure header.
+///
+typedef struct {
+  UINT8                          Type;
+  UINT8                          Length;
+  UINT16                         Handle;
+} SMBIOS_STRUCTURE;
+#endif
+
+///
+/// Firmware Version Information HOB Structure
+///
+typedef struct {
+  EFI_HOB_GUID_TYPE              Header;                    ///< Offset 0-23  The header of FVI HOB
+  SMBIOS_STRUCTURE               SmbiosData;                ///< Offset 24-27  The SMBIOS header of FVI HOB
+  UINT8                          Count;                     ///< Offset 28    Number of FVI elements included.
+///
+/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
+///
+} FIRMWARE_VERSION_INFO_HOB;
+#pragma pack()
+
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h
new file mode 100644
index 0000000..f99c3bc
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h
@@ -0,0 +1,17 @@
+/** @file
+  Intel FSP definition from Intel Firmware Support Package External
+  Architecture Specification v2.2.
+ @copyright
+  Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FSP_EAS_H_
+#define _FSP_EAS_H_
+
+#include <Uefi.h>
+#include <Guid/GuidHobFspEas.h>
+#include <Guid/FspHeaderFile.h>
+#include <FspEas/FspApi.h>
+
+#endif // _FSP_EAS_H_
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h
new file mode 100644
index 0000000..603db144
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h
@@ -0,0 +1,83 @@
+/** @file
+  FSP Error Information HOB to describe errors inside FSP that bootloader may
+  take some actions to handle those error scenarios.
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 2022 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _FSP_ERROR_INFO_HOB_H_
+#define _FSP_ERROR_INFO_HOB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+#include <Pi/PiStatusCode.h>
+
+#define FSP_ERROR_INFO_HOB_GUID                 { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 }}
+
+#pragma pack(1)
+
+typedef struct {
+  ///
+  /// GUID HOB header.
+  ///
+  EFI_HOB_GUID_TYPE     GuidHob;
+
+  ///
+  /// ReportStatusCode () type identifier.
+  ///
+  EFI_STATUS_CODE_TYPE  Type;
+
+  ///
+  /// ReportStatusCode () value.
+  ///
+  EFI_STATUS_CODE_VALUE Value;
+
+  ///
+  /// ReportStatusCode () Instance number.
+  ///
+  UINT32                Instance;
+
+  ///
+  /// Optional GUID which may be used to identify
+  /// which internal component of the FSP was
+  /// executing at the time of the error.
+  ///
+  EFI_GUID              CallerId;
+
+  ///
+  /// GUID identifying the nature of the fatal error.
+  ///
+  EFI_GUID              ErrorType;
+
+  ///
+  /// EFI_STATUS code describing the error encountered.
+  ///
+  UINT32                Status;
+} FSP_ERROR_INFO_HOB;
+
+#pragma pack()
+
+#endif //#ifndef _FSP_ERROR_INFO_HOB_H_
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h
new file mode 100644
index 0000000..ce86ce8
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h
@@ -0,0 +1,48 @@
+/** @file
+
+Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE               0x545F445055525053        /* 'SPRUPD_T' */
+
+#define FSPM_UPD_SIGNATURE               0x4D5F445055525053        /* 'SPRUPD_M' */
+
+#define FSPS_UPD_SIGNATURE               0x535F445055525053        /* 'SPRUPD_S' */
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h
new file mode 100644
index 0000000..bfd8d7d
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h
@@ -0,0 +1,1308 @@
+/** @file
+
+Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+#include <IioPcieConfigUpd.h>
+
+#pragma pack(1)
+
+
+/** FSP-M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Customer Revision
+  The Customer can set this revision string for their own purpose.
+**/
+  UINT8                       CustomerRevision[32];
+
+/** Offset 0x0060 - Bus Ratio
+  Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO
+**/
+  UINT8                       BusRatio[8];
+
+/** Offset 0x0068 - D2K Credit Config
+  Set the D2K Credit Config - 1: Min, <b>2: Med(Default)</b>, 3: Max.
+  1:Min, 2:Med, 3:Max
+**/
+  UINT8                       D2KCreditConfig;
+
+/** Offset 0x0069 - Snoop Throttle Config
+  Set the Snoop Throttle Config - <b>0: DIS(Default)</b>, 1: Min, 2: Med, 3: Max.
+  0:DIS, 1:Min, 2:Med, 3:Max
+**/
+  UINT8                       SnoopThrottleConfig;
+
+/** Offset 0x006A - Legacy VGA Soc
+  Socket that claims the legacy VGA range
+**/
+  UINT8                       LegacyVgaSoc;
+
+/** Offset 0x006B - Legacy VGA Stack
+  Stack that claims the legacy VGA range
+**/
+  UINT8                       LegacyVgaStack;
+
+/** Offset 0x006C - Pcie P2P Performance Mode
+  Determine if to enable PCIe P2P Performance Mode - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       P2pRelaxedOrdering;
+
+/** Offset 0x006D - UPI Debug Print Level
+  UPI Debug Print Level Bitmask - 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8:
+  Detail, <b>0x0F: All(Default)</b>.
+  1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All
+**/
+  UINT8                       DebugPrintLevel;
+
+/** Offset 0x006E - NumaEn
+  NumaEn - <b>1: Enable Numa(Default)</b>, 0: Disable Numa.
+  0:Disable, 1:Enable
+**/
+  UINT8                       NumaEn;
+
+/** Offset 0x006F - SNC
+  Enable or Disable SNC - 0: Disable, 2: Snc2, 4: Snc4, <b>0x0F: Auto(Default)</b>.
+  0: Disable, 2: Snc2, 4: Snc4, 0x0F: Auto
+**/
+  UINT8                       SncEn;
+
+/** Offset 0x0070 - UMA Clustering
+  Set UMA Clusters - 0: Disable, 2: Two Clusters, <b>4: Four Clusters(Default)</b>.
+  0:Disable, 2:Two Clusters, 4:Four Clusters
+**/
+  UINT8                       UmaClustering;
+
+/** Offset 0x0071 - IODC Mode
+  IODC Mode - 0: Disable, <b>1: Auto(Default)</b>, 2: Push, 3: AllocFlow, 4: NonAlloc,
+  5: WCILF.
+  0:Disable, 1:Auto, 2:Push, 3:AllocFlow, 4:NonAlloc, 5:WCILF
+**/
+  UINT8                       IoDcMode;
+
+/** Offset 0x0072 - Degrade Precedence
+  Setup Degrade Precedence - <b>0: Topology(Default)</b>, 1: Feature.
+  0:Topology, 1:Feature
+**/
+  UINT8                       DegradePrecedence;
+
+/** Offset 0x0073 - Degrade 4 Socket Preference
+  Setup Degrade 4 Socket Preference - <b>0: Fully Connect(Default)</b>, 1: Dual Link Ring.
+  0:Fully Connect, 1:Dual Link Ring
+**/
+  UINT8                       Degrade4SPreference;
+
+/** Offset 0x0074 - Directory Mode
+  Enable or Disable Directory Mode - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       DirectoryModeEn;
+
+/** Offset 0x0075 - XPT Prefetch Enable
+  Enable or Disable XPT Prefetch - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       XptPrefetchEn;
+
+/** Offset 0x0076 - KTI Prefetch Enable
+  Enable or Disable KTI Prefetch - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       KtiPrefetchEn;
+
+/** Offset 0x0077 - XPT Remote Prefetch Enable
+  Enable or Disable XPT Remote Prefetch Enable - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       XptRemotePrefetchEn;
+
+/** Offset 0x0078 - KTI FPGA
+  Enable or Disable KTI FPGA
+**/
+  UINT8                       KtiFpgaEnable[8];
+
+/** Offset 0x0080 - DDRT QoS Mode
+  DDRT QoS - <b>0: Mode 0(Default)</b>, 1: Mode 1, 2: Mode 2.
+  0:Mode 0, 1:Mode 1, 2:Mode 2
+**/
+  UINT8                       DdrtQosMode;
+
+/** Offset 0x0081 - KTI Link Speed Mode
+  Choose KTI Link Speed Mode - 0: Slow, <b>1: Full(Default)</b>.
+  0:Slow, 1:Full
+**/
+  UINT8                       KtiLinkSpeedMode;
+
+/** Offset 0x0082 - KTI Link Speed
+  Setup KTI Link Speed - 0: 128GT, 1: 144GT, 2: 160GT, 3: 200GT, <b>0x7F: Max KTI
+  Link Speed (Default)</b>, 0x8F: Frequency Per Link.
+  0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7F:Max KTI Link Speed, 0x8F:Frequency Per Link
+**/
+  UINT8                       KtiLinkSpeed;
+
+/** Offset 0x0083 - KTI Link L0p
+  Enable or Disable KTI Link L0p - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+  0:Disable, 1:Enable, 2: Auto
+**/
+  UINT8                       KtiLinkL0pEn;
+
+/** Offset 0x0084 - KTI Link L1
+  Enable or Disable KTI Link L1 - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+  0:Disable, 1:Enable, 2: Auto
+**/
+  UINT8                       KtiLinkL1En;
+
+/** Offset 0x0085 - Kti Link Speed Per Port
+  Setup KTI Link Speed to be allocated for each port - 0: 128GT, 1: 144GT, 2: 160GT,
+  3: 200GT, <b>0x7f: Max KTI Link Speed(Default)</b>.
+  0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7f:Max KTI Link Speed
+**/
+  UINT8                       KtiLinkSpeedPerPort[48];
+
+/** Offset 0x00B5 - DfxL0p Enable
+  Indicates the DfxL0p Enable to be allocated for each port - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       DfxL0pEnable[48];
+
+/** Offset 0x00E5 - DfxL1 Enable
+  Indicates the DfxL1 Enable to be allocated for each port - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       DfxL1Enable[48];
+
+/** Offset 0x0115 - KTI Failover
+  Enable or Disable KTI Failover - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>.
+  0:Disable, 1:Enable, 2: Auto
+**/
+  UINT8                       KtiFailoverEn;
+
+/** Offset 0x0116 - KTI LB Enable
+  Enable or Disable KTI LB - <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       KtiLbEn;
+
+/** Offset 0x0117 - KTI CRC Mode
+  Select KTI CRC Mode - <b>0: 16bit(Default)</b>, 1: 32bit, 2: Auto.
+  0:16bit, 1:32bit, 2:Auto
+**/
+  UINT8                       KtiCrcMode;
+
+/** Offset 0x0118 - KTI CPU Socket Hotplug
+  Enable or Disable KTI CPU Socket Hotplug - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       KtiCpuSktHotPlugEn;
+
+/** Offset 0x0119 - KTI CPU Socket HotPlug Topology
+  Select KTI CPU Socket HotPlug Topology - <b>0: 4Socket(Default)</b>, 1: 8Socket.
+  0:4Socket, 1:8Socket
+**/
+  UINT8                       KtiCpuSktHotPlugTopology;
+
+/** Offset 0x011A - KTI SKU Mismatch Check
+  Enable or Disable KTI SKU Mismatch Check - 0: Disable, <b>1 :Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       KtiSkuMismatchCheck;
+
+/** Offset 0x011B - TOR Threshold - Loctorem threshold Normal
+  Select TOR Threshold - Loctorem threshold Normal - 0: Disable, <b>1: Auto(Default)</b>,
+  2: Low, 3: Medium, 4: High.
+  0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
+**/
+  UINT8                       TorThresLoctoremNorm;
+
+/** Offset 0x011C - TOR threshold - Loctorem threshold empty
+  Select TOR threshold - Loctorem threshold empty - 0: Disable, <b>1: Auto(Default)</b>,
+  2: Low, 3: Medium, 4:High.
+  0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
+**/
+  UINT8                       TorThresLoctoremEmpty;
+
+/** Offset 0x011D - TSC Sync in Sockets
+  Enable or Disable TSC Sync in Sockets - 0: Disable, <b>1: Enable(Default)</b>, 2: Auto.
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       TscSyncEn;
+
+/** Offset 0x011E - HA A to S directory optimization
+  Enable or Disable HA A to S directory optimization - 0: Disable, 1: Enable, <b>2:
+  Auto(Default)</b>.
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       StaleAtoSOptEn;
+
+/** Offset 0x011F - LLC Deadline Allocation
+  Enable or Disable LLC Deadline Allocation - 0: Disable, <b>1: Enable(Default)</b>, 2: Auto.
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       LLCDeadLineAlloc;
+
+/** Offset 0x0120 - MBA BW Calibration Profiles
+  Choice of MBA BW throttling curve - 0: Linear BW shaping, 1: Biased BW shaping,
+  2: Legacy BW shaping, <b>3: Auto(Default)</b>.
+  0:Linear BW shaping, 1:Biased BW shaping, 2:Legacy BW shaping, 3:Auto
+**/
+  UINT8                       MbeBWCalChoice;
+
+/** Offset 0x0121 - Split Lock
+  Enable or Disable Split Lock - <b>0: Disable(Default)</b>, 1: Enable, 2: Auto.
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       SplitLock;
+
+/** Offset 0x0122 - Affinitize M2Iosf to Upi for 2-Socket
+  Affinitize M2IOSF traffic to proper UPI links to improve 2-Socket P2P perf - 0:
+  Disable, 1: Enable, <b>2: Auto(Default)</b>.
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       M2iosfToUpiAffinity;
+
+/** Offset 0x0123 - MMCFG Base Address
+  Setup MMCFG Base Address - 0: 1G, 1: 1.5G, 2: 1.75G, 3: 2G, 4: 2.25G, 5: 3G, <b>6:
+  Auto(Default)</b>.
+  0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto
+**/
+  UINT8                       mmCfgBase;
+
+/** Offset 0x0124 - MMCFG Size
+  Select MMCFG Size - 0: 64M, 1: 128M, 2: 256M, 3: 512M, 4: 1G, 5: 2G, <b>6: Auto(Default)</b>.
+  0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6:Auto
+**/
+  UINT8                       mmCfgSize;
+
+/** Offset 0x0125
+**/
+  UINT8                       UnusedUpdSpace0[3];
+
+/** Offset 0x0128 - MMIO High Base Address
+  MMIO High Base Address, a hex number for Bit[51:32]
+**/
+  UINT32                      mmiohBase;
+
+/** Offset 0x012C - CPU Physical Address Limit
+  CPU Physical Address Limit - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       CpuPaLimit;
+
+/** Offset 0x012D
+**/
+  UINT8                       UnusedUpdSpace1;
+
+/** Offset 0x012E - MMIO High Size
+  MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space
+  per CPU.  Range 1-1024
+**/
+  UINT16                      mmiohSize;
+
+/** Offset 0x0130 - isocEn
+  Enable or Disable isocEn - <b>0: Disable(Default)</b>, 1: Enable, 2: Auto.
+  0:Disable, 1:Enable, 2:Auto
+**/
+  UINT8                       isocEn;
+
+/** Offset 0x0131 - DCA
+  Enable or Disable DCA - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       dcaEn;
+
+/** Offset 0x0132
+**/
+  UINT8                       UnusedUpdSpace2[2];
+
+/** Offset 0x0134 - BoardTypeBitmask
+  BoardTypeBitmask
+**/
+  UINT32                      BoardTypeBitmask;
+
+/** Offset 0x0138 - AllLanesPtr
+  Pointer to array of ALL_LANES_EPARAM_LINK_INFO
+**/
+  UINT32                      AllLanesPtr;
+
+/** Offset 0x013C - PerLanePtr
+  Pointer to array of PER_LANE_EPARAM_LINK_INFO
+**/
+  UINT32                      PerLanePtr;
+
+/** Offset 0x0140 - AllLanesSizeOfTable
+  Number of elements in AllLanesPtr array.
+**/
+  UINT32                      AllLanesSizeOfTable;
+
+/** Offset 0x0144 - PerLaneSizeOfTable
+  Number of elements in PerLanePtr array.
+**/
+  UINT32                      PerLaneSizeOfTable;
+
+/** Offset 0x0148 - WaitTimeForPSBP
+  Enable or Disable WaitTimeForPSBP
+**/
+  UINT32                      WaitTimeForPSBP;
+
+/** Offset 0x014C - WaSerializationEn
+  Enable or Disable WaSerializationEn - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       WaSerializationEn;
+
+/** Offset 0x014D - KtiInEnableMktme
+  Enable or Disable KtiInEnableMktme - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       KtiInEnableMktme;
+
+/** Offset 0x014E - HIOP STACK DISABLE
+  Enables/Disables given HIOP STACK. Default is AUTO no stack is disabled. 1 - The
+  stacks indicated by the bit locations are disabled. 0 - The stacks indicated by
+  the bit locations are not modified. The stack order is abstracted each bit 0 =
+  stack 0 ... bit n = stack n. The bit setting for each stack can be overriden by
+  BIOS based on part-knob compatibility. The array size must be MAX_SOCKET x UINT32.
+**/
+  UINT8                       StackDisableBitMap[32];
+
+/** Offset 0x016E - CFRS3mProvision
+  Enable or Disable Provision S3M CFR - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       CFRS3mProvision;
+
+/** Offset 0x016F - CFRS3mManualCommit
+  Enable or Disable Manual Commit S3M FW CFR - <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       CFRS3mManualCommit;
+
+/** Offset 0x0170 - CFRPucodeProvision
+  Enable or Disable Provision PUcode CFR - <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       CFRPucodeProvision;
+
+/** Offset 0x0171 - CFRPucodeManualCommit
+  Enable or Disable Manual Commit PUcode CFR - <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       CFRPucodeManualCommit;
+
+/** Offset 0x0172
+**/
+  UINT8                       UnusedUpdSpace3[2];
+
+/** Offset 0x0174 - CFRImagePtr
+  Pointer to array of CFR Image
+**/
+  UINT32                      CFRImagePtr;
+
+/** Offset 0x0178 - Processor VmxEnable Function
+  Enable(Default) or Disable Processor VmxEnable Function - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       VmxEnable;
+
+/** Offset 0x0179 - Processor X2apic Function
+  Enable(Default) or Disable Processor X2apic Function - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       X2apic;
+
+/** Offset 0x017A - Processor HyperThreading Function
+  Enable(Default) or Disable Processor HyperThreading Function - 1: Disable, <b>0:
+  Enable(Default)</b>.
+  1:Disable, 0:Enable
+**/
+  UINT8                       ProcessorHyperThreadingDisable;
+
+/** Offset 0x017B - Processor Dynamic Intel Speed Select (ISS) Function
+  Enable or Disable(Default) Processor Dynamic Intel Speed Select (ISS) Function -
+  <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       ProcessorDynamicIssEnable;
+
+/** Offset 0x017C - Enables Intel(R) TXT
+  Enable or Disable(Default) Enables Intel(R) TXT - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       ProcessorLtsxEnable;
+
+/** Offset 0x017D - DDR frequency limit
+  Select DDR frequency limit, <b>0x00: Auto(Default)</b>, 0x13:DDR_3200, 0x16:DDR_3600,
+  0x19:DDR_4000, 0x1C:DDR_4400, 0x1D:DDR_4800, 0x1E:DDR_5200, 0x1F:DDR_5600
+**/
+  UINT8                       DdrFreqLimit;
+
+/** Offset 0x017E - Memory Serial Debug Message Level
+  Select Memory Serial Debug Message Level - 0: Disable, 1: Minimum, 2: Normal, <b>3:
+  Maximum(Default)</b>, 4: Auto.
+  0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto
+**/
+  UINT8                       serialDebugMsgLvl;
+
+/** Offset 0x017F - IIO ConfigIOU0
+  ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+  UINT8                       IioConfigIOU0[8];
+
+/** Offset 0x0187 - IIO ConfigIOU1
+  ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+  UINT8                       IioConfigIOU1[8];
+
+/** Offset 0x018F - IIO ConfigIOU2
+  ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+  UINT8                       IioConfigIOU2[8];
+
+/** Offset 0x0197 - IIO ConfigIOU3
+  ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+  UINT8                       IioConfigIOU3[8];
+
+/** Offset 0x019F - IIO ConfigIOU4
+  ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+  UINT8                       IioConfigIOU4[8];
+
+/** Offset 0x01A7 - IIO ConfigIOU5
+  ConfigIOU[MAX_SOCKET][5]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+  UINT8                       IioConfigIOU5[8];
+
+/** Offset 0x01AF - IIO ConfigIOU6
+  ConfigIOU[MAX_SOCKET][6]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+  0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+  UINT8                       IioConfigIOU6[8];
+
+/** Offset 0x01B7
+**/
+  UINT8                       UnusedUpdSpace4;
+
+/** Offset 0x01B8 - IIO PCIE Config Table Ptr
+  Pointer to array of UPD_IIO_PCIE_PORT_CONFIG
+**/
+  UINT32                      IioPcieConfigTablePtr;
+
+/** Offset 0x01BC - IIO PCIE Config Table Number
+  Number of elements in IioPcieConfigTablePtr array, socket number as unit.
+**/
+  UINT32                      IioPcieConfigTableNumber;
+
+/** Offset 0x01C0 - IIO DeEmphasis Array Ptr
+  Pointer to array of DeEmphasis
+**/
+  UINT32                      DeEmphasisPtr;
+
+/** Offset 0x01C4 - IIO DeEmphasis Array Number
+  Number of elements in DeEmphasis array.
+**/
+  UINT32                      DeEmphasisNumber;
+
+/** Offset 0x01C8 - IIO PCIe Common Clock Array Ptr
+  Pointer to array of PCIe Common Clock
+**/
+  UINT32                      PcieCommonClockPtr;
+
+/** Offset 0x01CC - IIO PCIe Common Clock Array Number
+  Number of elements in PCIe Common Clock array.
+**/
+  UINT32                      PcieCommonClockNumber;
+
+/** Offset 0x01D0 - VT-d Support
+  Enable or Disable VT-d Support - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       VtdSupport;
+
+/** Offset 0x01D1 - PCIe ACSCTL
+  Enable/Disable overwrite of PCI Access Control Services Control register in PCI
+  root ports - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       VtdPciAcsCtlWaEn;
+
+/** Offset 0x01D2
+**/
+  UINT8                       UnusedUpdSpace5[2];
+
+/** Offset 0x01D4 - IIO PCIe Port Hide Array Ptr
+  Pointer to array of Hide or visible for IIO Pcie Port.
+**/
+  UINT32                      PEXPHIDEPtr;
+
+/** Offset 0x01D8 - IIO PCIe Port Hide Array Number
+  Number of elements in IIO PCIe Port Hide Array.
+**/
+  UINT32                      PEXPHIDENumber;
+
+/** Offset 0x01DC - PcieHotPlugEnable
+  Enable or disable Pcie hot plug enable feature - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       PcieHotPlugEnable;
+
+/** Offset 0x01DD
+**/
+  UINT8                       UnusedUpdSpace6;
+
+/** Offset 0x01DE - DelayAfterPCIeLinkTraining
+  Custom delay after PCI-E link training on IIO ports
+**/
+  UINT16                      DelayAfterPCIeLinkTraining;
+
+/** Offset 0x01E0 - IIO PCI bus resource Ptr
+  Pointer to array of socket PCI bus resource.
+**/
+  UINT32                      PciBusResConfigPtr;
+
+/** Offset 0x01E4 - IIO PCI IO/MMIO base and limits resource Ptr
+  Pointer to array of socket PCI IO/MMIO resource.
+**/
+  UINT32                      PciBaseLimitsResConfigPtr;
+
+/** Offset 0x01E8 - PCH PCIE PLL Ssc
+  Pointer to array of socket PCI IO/MMIO resource.
+**/
+  UINT8                       PchPciePllSsc;
+
+/** Offset 0x01E9 - MeUmaEnable
+  Enable or disable ME UMA feature - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       MeUmaEnable;
+
+/** Offset 0x01EA - SerialIoUartDebugEnable
+  Enable or Disable SerialIo Uart debug library in FSP - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       SerialIoUartDebugEnable;
+
+/** Offset 0x01EB
+**/
+  UINT8                       UnusedUpdSpace7;
+
+/** Offset 0x01EC - ISA Serial Base selection
+  Select ISA Serial Base address could be initialized by boot loader - 0x2F8: 0x2F8,
+  <b>0x3F8: 0x3F8(Default)</b>.
+  0x2F8:0x2F8, 0x3F8:0x3F8
+**/
+  UINT16                      SerialIoUartDebugIoBase;
+
+/** Offset 0x01EE - MemRefreshWaterMark
+  Enable or Disable MemRefreshWaterMark in FSP - <b>0: Auto(Default)</b>, 1: Enable,
+  2: Disable.
+  0:Auto, 1:Enable, 2:Disable
+**/
+  UINT8                       PanicWm;
+
+/** Offset 0x01EF - promoteMrcWarnings
+  Enable or Disable MRC promote warning in FSP - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       promoteMrcWarnings;
+
+/** Offset 0x01F0 - promoteWarnings
+  <b>Enable(Default)</b> or Disable Promote warning in FSP - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       promoteWarnings;
+
+/** Offset 0x01F1 - serialDebugMsgLvlTrainResults
+  Enable or Disable Promote warning in FSP - <b>0:Disable(Default)</b>, 8:Enable.
+  0:Disable, 8:Enable
+**/
+  UINT8                       serialDebugMsgLvlTrainResults;
+
+/** Offset 0x01F2 - MemTest
+  <b>Enable(Default)</b> or Disable memory test during normal boot in FSP - 0: Disable,
+  <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       HwMemTest;
+
+/** Offset 0x01F3
+**/
+  UINT8                       UnusedUpdSpace8;
+
+/** Offset 0x01F4 - MemTest Loops
+  Number of memory test loops during normal boot, set to 0 to run memtest infinitely
+  in FSP - <b> 1 (Default)</b>.
+  minimum = 0, maximum = 65535
+**/
+  UINT16                      MemTestLoops;
+
+/** Offset 0x01F6
+**/
+  UINT8                       UnusedUpdSpace9[2];
+
+/** Offset 0x01F8 - Adv MemTest Options
+  This option is a bit mask[19:0]: All 0 = disabled: bit-0=XMATS8, bit-1=XMATS16,
+  bit-2=Reserved, bit-3=Reserved, bit-4=WCMATS8, bit-5=WCMCH8, bit-6=Reserved, bit-7=MARCHCM64,
+  bit-8=Reserved, bit-9=Reserved, bit-10=Reserved, bit-11=TWR, bit-12=DATARET, bit-13=MATS8TC1,
+  bit-14=MATS8TC2, bit-15=MATS8TC3, bit-16=SK-HYNIX, bit-17=SAMSUNG, bit-18=MICRON-RMW,
+  bit-19=SCRAM_X2 in FSP.
+**/
+  UINT32                      AdvMemTestOptions;
+
+/** Offset 0x01FC - SmartTestKey
+  Number of SmartTest Key
+**/
+  UINT32                      SmartTestKey;
+
+/** Offset 0x0200 - Adv MemTest Pause
+  Specify a pause delay between 0 to 256000 in units of usec. This is a time period
+  where refresh is disabled between write and read sequences in FSP.
+**/
+  UINT32                      AdvMemTestCondPause;
+
+/** Offset 0x0204 - Adv MemTest tREFI
+  Specify tREFI (refresh rate) timing between 1850 to 7800 in nsec.
+**/
+  UINT16                      AdvMemTestCondTrefi;
+
+/** Offset 0x0206 - Adv MemTest tWR
+  Specify tWR timing between 48 to 96 in units of tCK in FSP.
+**/
+  UINT8                       AdvMemTestCondTwr;
+
+/** Offset 0x0207
+**/
+  UINT8                       UnusedUpdSpace10;
+
+/** Offset 0x0208 - Adv MemTest PMIC VDD Level
+  Specify PMIC VDD level in units of mV in FSP.
+**/
+  UINT16                      AdvMemTestCondPmicVdd;
+
+/** Offset 0x020A - Adv MemTest Conditions
+  Auto = set test conditions based on test type; Manual = specify global test conditions;
+  Disable = Do not apply test conditions in FSP - 0: Disable, <b>1: Auto(Default)</b>,
+  2: Manual.
+  0:Disable, 1:Auto, 2:Manual
+**/
+  UINT8                       AdvMemTestCondition;
+
+/** Offset 0x020B - Adv MemTest Reset Failure Tracking List
+  Enable/disable Reset of the Row Failure Tracking List after each Adv MemTest option.
+  Useful for testing performance of multiple options in FSP - <b>0: Disable(Default)</b>,
+  1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       AdvMemTestResetList;
+
+/** Offset 0x020C - MemTest On Cold Fast Boot
+  Enable - Enables memory test during cold fast boot. Disable - Disables this feature.
+  Auto - Sets it to the MRC default setting; current default is Disable in FSP -
+  <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       MemTestOnColdFastBoot;
+
+/** Offset 0x020D - Attempt Fast Boot
+  Enable - Portions of memory reference code will be skipped when possible to increase
+  boot speed on warm boots. Disable - Disables this feature. Auto - Sets it to the
+  MRC default setting - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       AttemptFastBoot;
+
+/** Offset 0x020E - MemTest On Cold Fast Boot
+  Enable - Enables memory test during cold fast boot. Disable - Disables this feature.
+  Auto - Sets it to the MRC default setting - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       AttemptFastBootCold;
+
+/** Offset 0x020F - Multithreaded Memory Training
+  Selects the number of processor sockets to train in parallel. - <b>0: All sockets
+  operate in parallel(Default)</b>. 1: At any time only one socket is executing.
+  2: At any time only two socket are executing. 4: At any time only four socket are
+  executing in FSP.
+  0:All Processor Sockets, 1:One Socket at a Time (No Multithreading), 2:Two Sockets
+  at a Time, 4:Four Sockets at a Time
+**/
+  UINT8                       AllowedSocketsInParallel;
+
+/** Offset 0x0210 - Auto-Reset on mem Training Error
+  Enable/Disable Auto-Reset on mem Training Error in FSP - <b>0:Disable(Default)</b>,
+  1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       AutoResetOnMemErr;
+
+/** Offset 0x0211 - Rank Margin Tool
+  Enable/Disable the Rank Margin Tool in FSP - <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       EnableRMT;
+
+/** Offset 0x0212 - RMT on Fast Cold Boot
+  Enable/Disable the Rank Margin Tool on a Fast Cold Boot in FSP - <b>0:Disable(Default)</b>,
+  1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       EnableRMTonFCB;
+
+/** Offset 0x0213 - Execute Jedecinit before RMT
+  Execute Jedecinit before Rank Margin Tool in FSP - <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       JedecInitBeforeRMT;
+
+/** Offset 0x0214 - Backside Margining
+  Enable/Disable margin test on the register or buffer backside in FSP - <b>0:Disable(Default)</b>,
+  1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       RMTBacksideMargining;
+
+/** Offset 0x0215 - CmdAll
+  Step size of CmdAll. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
+  2:2, 4:4, 8:8.
+  1:Auto, 2:2, 4:4, 8:8
+**/
+  UINT8                       RMTCmdAll;
+
+/** Offset 0x0216 - RMT Debug Messages
+  Enable/Disable the RMT debug messages in FSP - <b>2:Disable(Default)</b>, 5:Enable.
+  2:Disable, 5:Enable
+**/
+  UINT8                       RMTDebugMessages;
+
+/** Offset 0x0217 - RMT Display Tables
+  Enable/Disable displaying results as tables in FSP - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       RMTDisplayTables;
+
+/** Offset 0x0218 - RMT Loop Count
+  Exponential loop count for single rank test in FSP.
+**/
+  UINT8                       RMTLoopCount;
+
+/** Offset 0x0219
+**/
+  UINT8                       UnusedUpdSpace11[3];
+
+/** Offset 0x021C - Test Signal Bit Mask For RMT
+  Test signal bit mask for RMT in FSP.
+**/
+  UINT32                      TestSignalBitMaskRMT;
+
+/** Offset 0x0220 - RMT Per Bit Margining
+  Enable/Disable Per Bit Margining in FSP - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       RMTPerBitMargining;
+
+/** Offset 0x0221 - RMT Per CA Lane Margining
+  Enable/Disable Per CA Lane Margining in FSP - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       RMTPerCaLaneMargining;
+
+/** Offset 0x0222 - RMT Display Plots
+  Enable/Disable the display of per-bit results as plots in FSP - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       RMTPerDisplayPlots;
+
+/** Offset 0x0223 - RMT RxDqs
+  Step size of RxDqs. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto,(Default)</b>
+  2:2, 4:4, 8:8.
+  1:Auto, 2:2, 4:4, 8:8
+**/
+  UINT8                       RMTRxDqs;
+
+/** Offset 0x0224 - RMT RxVref
+  Step size of RxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto,(Default)</b>
+  2:2, 4:4, 8:8.
+  1:Auto, 2:2, 4:4, 8:8
+**/
+  UINT8                       RMTRxVref;
+
+/** Offset 0x0225 - RMT Scrambler
+  Enable or Disable scrambler during RMT test in FSP - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       RMTScrambler;
+
+/** Offset 0x0226 - RMT Step Size Override
+  Enable or Disable overriding the default step sizes in FSP - <b>0:Disable(Default)</b>,
+  1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       RMTStepSizeOverride;
+
+/** Offset 0x0227 - RMT TxDq
+  Step size of TxDq. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
+  2:2, 4:4, 8:8.
+  1:Auto, 2:2, 4:4, 8:8
+**/
+  UINT8                       RMTTxDq;
+
+/** Offset 0x0228 - RMT TxVref
+  Step size of TxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>,
+  2:2, 4:4, 8:8.
+  1:Auto, 2:2, 4:4, 8:8
+**/
+  UINT8                       RMTTxVref;
+
+/** Offset 0x0229 - DDR5 ECS
+  Enable/Disable DDR5 Error Check and Scrub (ECS) in FSP - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       ErrorCheckScrub;
+
+/** Offset 0x022A - Enforce Memory POR
+  0:Enforce POR - Enforces Plan Of Record restrictions for DDR5 frequency and voltage
+  programming. <b>2:Disable  - Disables this feature and user is able to run at higher
+  frequencies, specified in the DDR Frequency Limit field (limited by processor support)(Default)</b>.
+  0:Enforce POR, 2:Disabled
+**/
+  UINT8                       EnforceDdrMemoryFreqPor;
+
+/** Offset 0x022B - Enforce Population POR
+  Enable Memory Population POR Enforcement.  Selecting Enforce Validated Populations
+  will only allow populations that have been validated in FSP - <b>0:Disable(Default)</b>,
+  1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       EnforcePopulationPor;
+
+/** Offset 0x022C - DDR PPR Type
+  Selects DDR Post Package Repair Type - 2: Hard PPR, <b>1: Soft PPR (Default)</b>,
+  0: Disabled.
+  0:Disabled, 2:Hard PPR, 1:Soft PPR
+**/
+  UINT8                       pprType;
+
+/** Offset 0x022D - Force PPR On All Dram for UCE
+  Force PPR on all dram for UCE in FSP - <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disabled, 1:Enabled
+**/
+  UINT8                       ForcePprOnAllDramUce;
+
+/** Offset 0x022E
+**/
+  UINT8                       UnusedUpdSpace12[2];
+
+/** Offset 0x0230 - pprAddrVariablePtr
+  Pointer to array of PPR_ADDR_VARIABLE
+**/
+  UINT32                      PprAddrVariablePtr;
+
+/** Offset 0x0234 - Allow Memory Test Correctable Error
+  Enable - Logs error and allows correctable errors during memory test(DIMM Rank not
+  removed). Disable - Logs error and removes DIMM Rank. Auto - Sets it to the MRC
+  default setting; current default is Enable in FSP - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       allowCorrectableMemTestError;
+
+/** Offset 0x0235 - Memory I/O Health Check
+  Memory I/O Health Check - 0: Auto, 1: Manual, <b>2: Disable (Default)</b>. Select
+  option Auto for default values. Manual for new values. Disable for disabling feature
+  in FSP - 0:Auto, 1:Manual, <b>2:Disable(Default)</b>.
+  0:Auto, 1:Manual, 2:Disable
+**/
+  UINT8                       MemIOHealthCheck;
+
+/** Offset 0x0236 - RxDqsDelay Left Edge
+  Offset for RxDqsDelay Left Edge in FSP.
+**/
+  UINT8                       CriticalRxDqsDelayLeftEdge;
+
+/** Offset 0x0237 - RxDqsDelay Right Edge
+  Offset for RxDqsDelay Right in FSP.
+**/
+  UINT8                       CriticalRxDqsDelayRightEdge;
+
+/** Offset 0x0238 - RxVref Left Edge
+  Offset for RxVref Left Edge in FSP.
+**/
+  UINT8                       CriticalRxVrefLeftEdge;
+
+/** Offset 0x0239 - RxVref Right Edge
+  Offset for RxVref Right Edge in FSP.
+**/
+  UINT8                       CriticalRxVrefRightEdge;
+
+/** Offset 0x023A - TxDqDelay Left Edge
+  Offset for TxDqDelay Left Edge in FSP.
+**/
+  UINT8                       CriticalTxDqDelayLeftEdge;
+
+/** Offset 0x023B - TxDqDelay Right Edge
+  Offset for TxDqDelay Right Edge in FSP.
+**/
+  UINT8                       CriticalTxDqDelayRightEdge;
+
+/** Offset 0x023C - TxVref Left Edge
+  Offset for TxDqDelay Left Edge in FSP.
+**/
+  UINT8                       CriticalTxVrefLeftEdge;
+
+/** Offset 0x023D - TxVref Right Edge
+  Offset for TxDqDelay Right Edge in FSP.
+**/
+  UINT8                       CriticalTxVrefRightEdge;
+
+/** Offset 0x023E - Reboot On Critical Failure
+  Reboot System on Critical failure to do Memory Training in FSP - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       ResetOnCriticalError;
+
+/** Offset 0x023F - Number of Times to Reboot and Retrain
+  Number of times to Reboot System on Critical failure to do Memory Training in FSP.
+**/
+  UINT8                       CriticalRetries;
+
+/** Offset 0x0240 - Memory I/O Health Check Loop Count
+  CPGC Test Loop Count for Memory IO Health Test
+**/
+  UINT8                       MemIOHealthLoopCount;
+
+/** Offset 0x0241 - Telemetry RxDqsDelay Left Edge
+  Offset for Telemetry RxDqsDelay Left Edge in FSP.
+**/
+  UINT8                       TelemetryRxDqsDelayLeftEdge;
+
+/** Offset 0x0242 - Telemetry RxDqsDelay Right Edge
+  Offset for Telemetry RxDqsDelay Right Edge in FSP.
+**/
+  UINT8                       TelemetryRxDqsDelayRightEdge;
+
+/** Offset 0x0243 - Telemetry RxVref Left Edge
+  Offset for Telemetry RxDqsDelay Left Edge in FSP.
+**/
+  UINT8                       TelemetryRxVrefLeftEdge;
+
+/** Offset 0x0244 - Telemetry RxVref Right Edge
+  Offset for Telemetry RxDqsDelay Right Edge in FSP.
+**/
+  UINT8                       TelemetryRxVrefRightEdge;
+
+/** Offset 0x0245 - Telemetry TxDqDelay Left Edge
+  Offset for Telemetry TxDqDelay Left Edge in FSP.
+**/
+  UINT8                       TelemetryTxDqDelayLeftEdge;
+
+/** Offset 0x0246 - Telemetry TxDqDelay Right Edge
+  Offset for Telemetry TxDqDelay Right Edge in FSP.
+**/
+  UINT8                       TelemetryTxDqDelayRightEdge;
+
+/** Offset 0x0247 - Volatile Memory Mode
+  Selects 1LM or 2LM mode for volatile memory. For 2LM memory mode, system will try
+  to configure 2LM but if system is unable to configure 2LM, volatile memory mode
+  will fall back to 1LM in FSP - <b>0: 1LM(Default)</b>, 1: 2LM, 2: MIX 1LM2LM.
+  0: 1LM, 1: 2LM, 2: MIX 1LM2LM
+**/
+  UINT8                       volMemMode;
+
+/** Offset 0x0248 - Dynamic ECC Mode Selection
+  Enable/Disable Dynamic ECC Mode Selection in FSP - 0:Disable, <b>1:Enable(Default)</b>,
+  2:Enable + Allow 128b ECC.
+  0:Disable, 1:Enable, 2:Enable + Allow 128b ECC
+**/
+  UINT8                       DynamicEccModeSel;
+
+/** Offset 0x0249 - Memory Patrol Scrub
+  Memory Patrol Scrub - 0:Disable, 1:Enable during FspMemoryInit(), <b>2:Enable during
+  NotifyPhase(EnumInitPhaseReadyToBoot) (Default)</b>.
+  0:Disable, 1:Enable during FspMemoryInit(), 2:Enable during EnumInitPhaseReadyToBoot
+**/
+  UINT8                       PatrolScrub;
+
+/** Offset 0x024A - Memory Patrol Scrub
+  Memory Patrol Scrub - <b>0:Disable  (Default)</b>, 1:Enable at ReadyToBootFsp().
+  0:Disable, 1:Enable Enable at ReadyToBootFsp()
+**/
+  UINT8                       PatrolScrubNotify;
+
+/** Offset 0x024B - Patrol Scrub Interval
+  Patrol Scrub Interval in FSP.
+**/
+  UINT8                       PatrolScrubDuration;
+
+/** Offset 0x024C - Patrol Scrub Address Mode
+  Selects the address mode between <b>1: System Physical Address (Default)</b>, 0:Reverse
+  Address in FSP.
+  0:Reverse Address, 1:System Physical Address
+**/
+  UINT8                       PatrolScrubAddrMode;
+
+/** Offset 0x024D - Memory Thermal Throttling Mode
+  Memory Configure Memory Thermal Throttling Mode in FSP - 0:Disable, <b>2:CLTT_ENABLE(Default)</b>,
+  3:CLTT_PECI_ENABLE.
+  0:Disable, 2:CLTT_ENABLE, 3:CLTT_PECI_ENABLE
+**/
+  UINT8                       thermalthrottlingsupport;
+
+/** Offset 0x024E - Memory Correctable Error Threshold
+  Memory Correctable Error Threshold (1 - 32767) used for sparing and leaky bucket in FSP.
+**/
+  UINT16                      spareErrTh;
+
+/** Offset 0x0250 - WR CRC feature Control
+  Enable/Disable Write CRC in FSP - <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       WrCRC;
+
+/** Offset 0x0251 - Adaptive Refresh Management Level
+  Selects Adaptive Refresh Management(ARFM) Level when refresh management(RFM) is
+  required. <b>0:Default - RAAIMT, RAAMMT, RAADEC(Default)</b>; 1:Level A - RAAIMT-A,
+  RAAMMT-A, RAADEC-A; 2:Level B - RAAIMT-B, RAAMMT-B, RAADEC-B; 3:Level C - RAAIMT-C,
+  RAAMMT-C, RAADEC-C
+  0:Default - RAAIMT; RAAMMT; RAADEC, 1:Level A - RAAIMT-A; RAAMMT-A; RAADEC-A, 2:Level
+  B - RAAIMT-B; RAAMMT-B; RAADEC-B, 3:Level C - RAAIMT-C; RAAMMT-C; RAADEC-C
+**/
+  UINT8                       AdaptiveRefreshMgmtLevel;
+
+/** Offset 0x0252 - MEMHOT INPUT Control
+  Enable/Disable MEMHOT INPUT in FSP - <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       MemHotIn;
+
+/** Offset 0x0253 - MEMHOT OUTPUT Mode
+  MEMHOT OUTPUT Mode in FSP - 0:Disable, <b>1:Enable only temphi(Default)</b>, 2:Enable
+  temphi & mid, 3:Enable temphi & mid & low.
+  0:Disable, 1:Enable only temphi, 2:Enable temphi & mid, 3:Enable temphi & mid & low
+**/
+  UINT8                       MemhotOutputOnlyOpt;
+
+/** Offset 0x0254 - CxlType3LegacyEn
+  Enable or disable CXL type 3 device using CXL type 2 flow - <b>0:Disable(Default)</b>, 1:Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       DfxCxlType3LegacyEn;
+
+/** Offset 0x0255 - DfxPmicSecureMode
+  0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, <b>2:Auto Pmic Secure Mode(Default)</b>.
+  0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode
+**/
+  UINT8                       DfxPmicSecureMode;
+
+/** Offset 0x0256 - IIO PcieSubSystemMode0
+  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
+  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+**/
+  UINT8                       IioPcieSubSystemMode0[8];
+
+/** Offset 0x025E - IIO PcieSubSystemMode1
+  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
+  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+**/
+  UINT8                       IioPcieSubSystemMode1[8];
+
+/** Offset 0x0266 - IIO PcieSubSystemMode2
+  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
+  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+**/
+  UINT8                       IioPcieSubSystemMode2[8];
+
+/** Offset 0x026E - IIO PcieSubSystemMode3
+  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
+  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+**/
+  UINT8                       IioPcieSubSystemMode3[8];
+
+/** Offset 0x0276 - IIO PcieSubSystemMode4
+  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
+  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+**/
+  UINT8                       IioPcieSubSystemMode4[8];
+
+/** Offset 0x027E - IIO PcieSubSystemMode5
+  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
+  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+**/
+  UINT8                       IioPcieSubSystemMode5[8];
+
+/** Offset 0x0286 - IIO PcieSubSystemMode6
+  PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5,
+  0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b>
+**/
+  UINT8                       IioPcieSubSystemMode6[8];
+
+/** Offset 0x028E - CXL Header Bypass
+  Enable/Disable the CXL header bypass in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
+  0:Disable, 1:Enable
+**/
+  UINT8                       DfxCxlHeaderBypass;
+
+/** Offset 0x028F - CXL Security Level
+  CXL Security Level<br>\n
+  0: Fully Trusted - CXL Device can get access on CXL.$ for host-attached and device
+  attached memory ranges in the WB address space.<br>\n
+  1: Partially Trusted - CXL Device can get access on CXL.$ for device attached memory
+  ranges only;<br>\n
+  2: Untrusted - All requests on CXL.$ will be aborted by the Host.<br>\n
+  <b>3: Auto - Currently identical to Fully Trusted. (Default)</b>
+  0:Fully Trusted, 1:Partially Trusted, 2:Untrusted, 3:Auto
+**/
+  UINT8                       DfxCxlSecLvl;
+
+/** Offset 0x0290
+**/
+  UINT32                      DfxCxlDebugModePtr;
+
+/** Offset 0x0294
+**/
+  UINT32                      DfxCxlDebugModeNumber;
+
+/** Offset 0x0298 - Lock Chipset
+  Lock or Unlock chipset in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
+  0:Disable, 1:Enable
+**/
+  UINT8                       LockChipset;
+
+/** Offset 0x0299 - MSR Lock Control
+  Enable - MSR 3Ah and CSR 80h will be locked in FSP. Power Good reset is needed to
+  remove lock bits - <b>0:Disabled(Default)</b>, 1:Enabled.
+  0:Disable, 1:Enable
+**/
+  UINT8                       ProcessorMsrLockControl;
+
+/** Offset 0x029A - DFX Enable
+  When Enabled, Expose IIO DFX devices and other CPU devices like PMON in FSP - <b>0:Disabled(Default)</b>,
+  1:Enabled.
+  0:Disable, 1:Enable
+**/
+  UINT8                       DFXEnable;
+
+/** Offset 0x029B - DFX Disable Bios Done
+  When Enabled, suppresses notifying processor via MSR 151h that boot initialization
+  is finished in FSP - <b>0:Disabled(Default)</b>, 1:Enabled.
+  0:Disable, 1:Enable
+**/
+  UINT8                       DfxDisableBiosDone;
+
+/** Offset 0x029C - Processor Package C State
+  Package C State - 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention)
+  state, 7: No Limit, <b>0xFF: Auto (Default)</b>
+  0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention) state,
+  7: No Limit, 0xFF: Auto
+**/
+  UINT8                       CpuPmPackageCState;
+
+/** Offset 0x029D - Enhanced Intel SpeedStep(R) Tech
+  Enhanced Intel SpeedStep(R) Tech - <b>1: Enable(Default)</b>, 0: Disable.
+  0:Disabled, 1:Enabled
+**/
+  UINT8                       CpuPmEistEnable;
+
+/** Offset 0x029E - C1E
+  C1E - <b>1: Enable(Default)</b>, 0: Disable.
+**/
+  UINT8                       CpuPmC1eEnable;
+
+/** Offset 0x029F - Intel SST-PP
+  Intel SST-PP Select allows user to choose level - <b>0xFF: Choose lowest level hardware
+  supported(Default)</b>, 0: Level 0, 3: Level 3, 4: Level 4.
+**/
+  UINT8                       CpuPmIssTdpLevel;
+
+/** Offset 0x02A0 - Activate SST-BF
+  SST-BF - <b>0: Disable (Default)</b>, 1: Enabled.
+  0:Disabled, 1:Enabled
+**/
+  UINT8                       CpuPmProcessorActivePbf;
+
+/** Offset 0x02A1
+**/
+  UINT8                       UnusedUpdSpace13[7];
+
+/** Offset 0x02A8 - Socket 0 Core Disable Bitmask
+  Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0. NOTE: Any core
+  disabled by user will force static SST-PP.
+**/
+  UINT64                      CpuPmCoreDisableBitmask0;
+
+/** Offset 0x02B0 - Socket 1 Core Disable Bitmask
+  Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1. NOTE: Any core
+  disabled by user will force static SST-PP.
+**/
+  UINT64                      CpuPmCoreDisableBitmask1;
+
+/** Offset 0x02B8
+**/
+  UINT8                       ReservedMemoryInitUpd[16];
+} FSPM_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSPM_ARCH_UPD               FspmArchUpd;
+
+/** Offset 0x0040
+**/
+  FSPM_CONFIG                 FspmConfig;
+
+/** Offset 0x02C8
+**/
+  UINT8                       UnusedUpdSpace14[6];
+
+/** Offset 0x02CE
+**/
+  UINT16                      UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h
new file mode 100644
index 0000000..79e0929
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h
@@ -0,0 +1,286 @@
+/** @file
+
+Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** FSP-S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0020 - Processor VmxEnable Function
+  Processor VmxEnable Function - <b>1: Enable(Default)</b>, 0: Disable Processor VmxEnable Function.
+  0: Disable, 1: Enable
+**/
+  UINT8                       VmxEnable;
+
+/** Offset 0x0021 - Processor TurboMode Function
+  Processor TurboMode Function - <b>1: Enable(Default)</b>, 0: Disable Processor TurboMode Function.
+  0: Disable, 1: Enable
+**/
+  UINT8                       TurboMode;
+
+/** Offset 0x0022 - Processor Safer Mode Extensions Function
+  Processor Safer Mode Extensions Function - <b>0: Disable(Default)</b>, 1: Enable
+  Processor Safer Mode Extensions Function.
+  0: Disable, 1: Enable
+**/
+  UINT8                       ProcessorSmxEnable;
+
+/** Offset 0x0023 - SstCp
+  SstCp - 1: Enable, <b>0: Disable SstCp(Default)</b>.
+  0: Disable, 1: Enable
+**/
+  UINT8                       SstCpSetting;
+
+/** Offset 0x0024 - SstCp Capable Status
+  SST-CP Capable Status in system - <b>0: Disable(Default)</b>, 1: Enable.
+  0: Disable, 1: Enable
+**/
+  UINT8                       SstCpCapableSystem;
+
+/** Offset 0x0025
+**/
+  UINT8                       UnusedUpdSpace0[1];
+
+/** Offset 0x0026 - PCH Protect Range Limit
+  Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+  limit comparison.
+**/
+  UINT16                      PchProtectedRangeLimit[5];
+
+/** Offset 0x0030 - PCH Protect Range Base
+  Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
+**/
+  UINT16                      PchProtectedRangeBase[5];
+
+/** Offset 0x003A - PchAdrEn
+  PchAdr - <b>0: PLATFORM POR(Default)</b>, 1: FORCE ENABLE, 2:FORCE DISABLE.
+  0: PLATFORM POR, 1: FORCE ENABLE, 2: FORCE DISABLE
+**/
+  UINT8                       PchAdrEn;
+
+/** Offset 0x003B - EnableTme
+  EnableTme - <b>0: Disabled(Default)</b>, 1: Enabled, 2:Software Controlled.
+  0: Disabled, 1: Enabled, 2:Software Controlled
+**/
+  UINT8                       EnableTme;
+
+/** Offset 0x003C - EnableTmeBypass
+  EnableTmeBypass - <b>0: Disabled(Default)</b>, 1: Enabled.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       EnableTmeBypass;
+
+/** Offset 0x003D - SgxFactoryReset
+  SgxFactoryReset - <b>0: Disabled(Default)</b>, 1: Enabled.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       SgxFactoryReset;
+
+/** Offset 0x003E - EnableSgx
+  EnableSgx - <b>0: Disabled(Default)</b>, 1: Enabled.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       EnableSgx;
+
+/** Offset 0x003F - SgxPackageInfoInBandAccess
+  SgxPackageInfoInBandAccess - <b>0: Disabled(Default)</b>, 1: Enabled.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       SgxPackageInfoInBandAccess;
+
+/** Offset 0x0040 - SgxQoS
+  SgxQoS - 0: Disabled, <b>1: Enabled(Default)</b>.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       SgxQoS;
+
+/** Offset 0x0041 - EpochUpdate
+  EpochUpdate - 1: Change to New Random Owner EPOCHs, <b>2: Manual User Defined Owner
+  EPOCHs(Default)</b>.
+  1: Change to New Random Owner EPOCHs, 2: Manual User Defined Owner EPOCHs
+**/
+  UINT8                       EpochUpdate;
+
+/** Offset 0x0042 - SgxLeWr
+  SgxLeWr - <b>0: Disabled(Default)</b>, 1: Enabled.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       SgxLeWr;
+
+/** Offset 0x0043 - SgxDebugMode
+  SgxDebugMode - <b>0: Disabled(Default)</b>, 1: Enabled.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       SgxDebugMode;
+
+/** Offset 0x0044 - SgxAutoRegistrationAgent
+  SgxAutoRegistrationAgent - <b>0: Disabled(Default)</b>, 1: Enabled.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       SgxAutoRegistrationAgent;
+
+/** Offset 0x0045 - DfxSgxRegistrationServerSelect
+  DfxSgxRegistrationServerSelect - <b>0: SBX(Default)</b>, 1: PRX, 2:AUTO, 3:LIV,
+  4:SW Defined Server.
+  0: SBX, 1: PRX, 2:AUTO, 3:LIV, 4:SW Defined Server
+**/
+  UINT8                       DfxSgxRegistrationServerSelect;
+
+/** Offset 0x0046 - Processor Enable Monitor MWAIT
+  Processor Enable Monitor MWAIT - <b>1: Enable(Default)</b>, 0: Disable Processor
+  Monitor MWAIT.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       CpuPmMonitorMWait;
+
+/** Offset 0x0047 - Processor C6
+  Processor C6 - <b>1: Enable(Default)</b>, 0: Disable Processor C6 (ACPI C3) report to OS.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       CpuPmC6Enable;
+
+/** Offset 0x0048 - Hardware P-States
+  Hardware P-States - 0:  Disable: Hardware chooses a P-state based on OS Request
+  (Legacy P-States), <b>1:Native Mode:Hardware chooses a P-state based on OS guidance(Default)</b>,
+  2:Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance), 3:Native
+  Mode with No Legacy Support.
+  0: Disable, 1: Native Mode, 2: Out of Band Mode, 3: Native Mode with No Legacy Support
+**/
+  UINT8                       CpuPmProcessorHWPMEnable;
+
+/** Offset 0x0049 - Power Performance Tuning
+  Power Performance Tuning - <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls
+  EPB, 2: PECI Controls EPB.
+  0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
+**/
+  UINT8                       CpuPmPwrPerfTuning;
+
+/** Offset 0x004A - Configure SST-BF
+  Allow (Default)/Disallow BIOS to configure SST-BF High Priority Cores so that SW
+  does not have to configure - 0:Disable, <b>1:Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       CpuPmProcessorConfigurePbf;
+
+/** Offset 0x004B - CF9 Global Reset Promotion
+  CF9 Global Reset Promotion - 1: Enable promoting CF9 reset to global, <b>0: Disable
+  promoting CF9 reset to global(Default)</b>.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       MeGrPromotionEnabled;
+
+/** Offset 0x004C - Global Reset Lock
+  Global Reset Lock - <b>1: Enable locking the joint ME and host reset capability(Default)</b>,
+  0: Disable locking the joint ME and host reset capability.
+  0: Disabled, 1: Enabled
+**/
+  UINT8                       MeGrLockEnabled;
+
+/** Offset 0x004D - Delayed Authentication Mode
+  Enable or disable Delayed Authentication Mode - <b>0: Disable(Default)</b>, 1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       DelayedAuthenticationMode;
+
+/** Offset 0x004E - Delayed Authentication Mode Override
+  Enable or disable Delayed Authentication Mode Override - <b>0: Disable(Default)</b>,
+  1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       DelayedAuthenticationModeOverride;
+
+/** Offset 0x004F - Core Bios Done Message
+  Enable or disable Core Bios Done message sent to ME - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       CoreBiosDoneEnabled;
+
+/** Offset 0x0050 - End Of Post Message
+  Enable or disable sending END_OF_POST message to ME - 0: Disable, 1: Send in PEI,
+  <b>2: Send in DXE(Default)</b>.
+  0:Disable, 1:Send in PEI, 2:Send in DXE
+**/
+  UINT8                       EndOfPostMessage;
+
+/** Offset 0x0051 - HMRFPO_LOCK Message
+  Enable or disable sending HMRFPO_LOCK message to ME - 0: Disable, <b>1: Enable(Default)</b>.
+  0:Disable, 1:Enable
+**/
+  UINT8                       MeHmrfpoLockEnabled;
+
+/** Offset 0x0052 - HMRFPO_ENABLE Message
+  Enable or disable sending HMRFPO_ENABLE message to ME - <b>0: Disable(Default)</b>,
+  1: Enable.
+  0:Disable, 1:Enable
+**/
+  UINT8                       MeHmrfpoEnableEnabled;
+
+/** Offset 0x0053
+**/
+  UINT8                       UnusedUpdSpace1[1];
+
+/** Offset 0x0054
+**/
+  UINT8                       ReservedSiliconInitUpd[16];
+} FSPS_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSPS_CONFIG                 FspsConfig;
+
+/** Offset 0x0064
+**/
+  UINT8                       UnusedUpdSpace2[2];
+
+/** Offset 0x0066
+**/
+  UINT16                      UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h
new file mode 100644
index 0000000..b887411
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h
@@ -0,0 +1,109 @@
+/** @file
+
+Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPTUPD_H__
+#define __FSPTUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+/** FSP-T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+  UINT32                      MicrocodeRegionBase;
+
+/** Offset 0x0024
+**/
+  UINT32                      MicrocodeRegionLength;
+
+/** Offset 0x0028
+**/
+  UINT32                      CodeRegionBase;
+
+/** Offset 0x002C
+**/
+  UINT32                      CodeRegionLength;
+
+/** Offset 0x0030
+**/
+  UINT8                       Reserved1[16];
+} FSPT_CORE_UPD;
+
+/** FSP-T Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Disable Port80 output in FSP-T
+  Select Port80 Control in FSP-T - 0:VPD-Style, <b>1:Enable Port80 Output (Default)</b>,
+  2:Disable Port80 Output, refer to FSP Integration Guide for details.
+  0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
+**/
+  UINT8                       FsptPort80RouteDisable;
+
+/** Offset 0x0041
+**/
+  UINT8                       ReservedTempRamInitUpd[31];
+} FSPT_CONFIG;
+
+/** Fsp T UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSPT_CORE_UPD               FsptCoreUpd;
+
+/** Offset 0x0040
+**/
+  FSPT_CONFIG                 FsptConfig;
+
+/** Offset 0x0060
+**/
+  UINT8                       UnusedUpdSpace0[6];
+
+/** Offset 0x0066
+**/
+  UINT16                      UpdTerminator;
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h
new file mode 100644
index 0000000..175dd75
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h
@@ -0,0 +1,143 @@
+/** @file
+  Header file to define the structures used for FSPM dynamic configuration.
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 2021 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _IIO_PCIE_CONFIG_UPD_H_
+#define _IIO_PCIE_CONFIG_UPD_H_
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET                  4
+#endif
+
+#ifndef MAX_LOGIC_IIO_STACK
+#define MAX_LOGIC_IIO_STACK        14
+#endif
+
+#ifndef MAX_IIO_PORTS_PER_SOCKET
+#define MAX_IIO_PORTS_PER_SOCKET   57
+#endif
+
+#ifndef MAX_IOU_PER_SOCKET
+#define MAX_IOU_PER_SOCKET         7
+#endif
+
+#define MAX_VMD_STACKS_PER_SOCKET          8  // Max number of stacks per socket supported by VMD
+
+#pragma pack(1)
+
+typedef struct {
+  UINT8    SLOTEIP[MAX_IIO_PORTS_PER_SOCKET];          // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
+  UINT8    SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET];        // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6)
+  UINT8    SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET];        // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
+  UINT8    SLOTPIP[MAX_IIO_PORTS_PER_SOCKET];          // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
+  UINT8    SLOTAIP[MAX_IIO_PORTS_PER_SOCKET];          // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
+  UINT8    SLOTMRLSP[MAX_IIO_PORTS_PER_SOCKET];        // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2)
+  UINT8    SLOTPCP[MAX_IIO_PORTS_PER_SOCKET];          // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1)
+  UINT8    SLOTABP[MAX_IIO_PORTS_PER_SOCKET];          // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
+  UINT8    SLOTIMP[MAX_IIO_PORTS_PER_SOCKET];
+  UINT8    SLOTSPLS[MAX_IIO_PORTS_PER_SOCKET];
+  UINT8    SLOTSPLV[MAX_IIO_PORTS_PER_SOCKET];
+  UINT16   SLOTPSP[MAX_IIO_PORTS_PER_SOCKET];
+  BOOLEAN  VppEnabled[MAX_IIO_PORTS_PER_SOCKET];        // 00 -- Disable, 01 -- Enable  //no setup option defined- aj
+  UINT8    VppPort[MAX_IIO_PORTS_PER_SOCKET];           // 00 -- Port 0, 01 -- Port 1   //no setup option defined- aj
+  UINT8    VppAddress[MAX_IIO_PORTS_PER_SOCKET];        // 01-07 for SMBUS address of Vpp   //no setup option defined- aj
+  UINT8    MuxAddress[MAX_IIO_PORTS_PER_SOCKET];        // SMBUS address of MUX              //no setup option defined
+  UINT8    ChannelID[MAX_IIO_PORTS_PER_SOCKET];         // 00 -- channel 0, 01 -- channel 1  //no setup option defined
+
+  UINT8    PciePortEnable[MAX_IIO_PORTS_PER_SOCKET];
+  UINT8    PEXPHIDE[MAX_IIO_PORTS_PER_SOCKET];          // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
+  UINT8    HidePEXPMenu[MAX_IIO_PORTS_PER_SOCKET];      // to suppress /display the PCIe port menu
+  UINT8    PciePortOwnership[MAX_IIO_PORTS_PER_SOCKET];
+  UINT8    RetimerConnectCount[MAX_IIO_PORTS_PER_SOCKET];
+  UINT8    ConfigIOU[MAX_IOU_PER_SOCKET];               // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4)
+  UINT8    PcieHotPlugOnPort[MAX_IIO_PORTS_PER_SOCKET]; // Manual override of hotplug for port
+  UINT8    VMDEnabled[MAX_VMD_STACKS_PER_SOCKET];
+  UINT8    VMDPortEnable[MAX_IIO_PORTS_PER_SOCKET];
+  UINT8    VMDHotPlugEnable[MAX_VMD_STACKS_PER_SOCKET];
+  UINT8    PcieMaxPayload[MAX_IIO_PORTS_PER_SOCKET];
+  UINT8    PciePortLinkSpeed[MAX_IIO_PORTS_PER_SOCKET]; // auto - 0(default); gen1 -1; gen2 -2; ... gen5 -5.
+  UINT8    DfxDnTxPresetGen3[MAX_IIO_PORTS_PER_SOCKET]; //auto - 0xFF(default); p0 - 0; p1 -1; ... p9 - 9.
+  UINT8    PcieGlobalAspm;
+  UINT8    PcieMaxReadRequestSize;
+} UPD_IIO_PCIE_PORT_CONFIG;
+
+typedef struct {
+  struct {
+    UINT8  Segment;                                  ///< Remember segment, if it changes reset everything
+    UINT8  StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack
+  } Socket[MAX_SOCKET];
+} SYSTEM_PCI_BUS_CONFIGURATION;
+
+typedef struct {
+  UINT64 Base;    ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions)
+  UINT64 Limit;   ///< Limit (last valid) address of a range
+} PCIE_BASE_LIMIT;
+
+typedef struct {
+  UINT32 MmioLSize;
+  UINT64 MmioHSize;
+} CXL11_LIMITS;
+
+typedef struct {
+  PCIE_BASE_LIMIT Io;        ///< Base and limit of I/O range assigned to entity
+  PCIE_BASE_LIMIT LowMmio;   ///< Base and limit of low MMIO region for entity
+  PCIE_BASE_LIMIT HighMmio;  ///< Base and limit of high (64-bit) MMIO region for entity
+} PCI_BASE_LIMITS;
+
+typedef struct {
+  PCI_BASE_LIMITS SocketLimits;                     ///< Base and Limit of all PCIe resources for the socket
+  PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
+  CXL11_LIMITS    CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
+} SOCKET_PCI_BASE_LIMITS;
+
+typedef struct {
+  //
+  // Save basic system configuration parameters along with the resource map to detect a change.
+  // Remember low and high I/O memory range when saving recource configuration. It is used to verify
+  // whether system memory map changed. Remember also stacks configured when creating the map.
+  // If anything changed reset the system PCI resource configuration.
+  //
+  UINT64                 MmioHBase;
+  UINT64                 MmioHGranularity;
+  UINT32                 MmioLBase;
+  UINT32                 MmioLLimit;
+  UINT32                 MmioLGranularity;
+  UINT16                 IoBase;
+  UINT16                 IoLimit;
+  UINT16                 IoGranularity;
+  UINT32                 StackPresentBitmap[MAX_SOCKET];
+  //
+  // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
+  // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
+  // which updates the KTI resource map.
+  //
+  SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET];        ///< Base and limit of all PCIe resources for each socket
+} SYSTEM_PCI_BASE_LIMITS;
+
+#pragma pack()
+
+#endif // _IIO_PCIE_CONFIG_UPD_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h
new file mode 100644
index 0000000..4857d4b
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h
@@ -0,0 +1,251 @@
+/** @file
+  Data format for IIO Universal Data HOB Structure
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 1999 - 2021 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
+#define _IIO_UNIVERSAL_DATA_HOB_H_
+
+#define IIO_UNIVERSAL_DATA_GUID { \
+  0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \
+  0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0  \
+}
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET                4
+#endif
+
+#if (MAX_SOCKET == 1)
+  #define MAX_FW_KTI_PORTS        4    // Maximum KTI PORTS to be used in structure definition.
+#else
+  #define MAX_FW_KTI_PORTS        6    // Maximum KTI PORTS to be used in structure definition
+#endif //(MAX_SOCKET == 1)
+
+#ifndef MAX_IMC
+#define MAX_IMC                   4    // Maximum memory controllers per socket
+#endif
+
+#ifndef MAX_MC_CH
+#define MAX_MC_CH                 2    // Max number of channels per MC (3 for EP)
+#endif
+
+#ifndef MAX_CH
+#define MAX_CH                    ((MAX_IMC)*(MAX_MC_CH))     // Max channels per socket (worst case EP * EX combination = 16)
+#endif
+
+#define MC_MAX_NODE               (MAX_SOCKET * MAX_IMC)  // Max number of memory nodes
+
+#ifndef MAX_IIO_PORTS_PER_SOCKET
+#define MAX_IIO_PORTS_PER_SOCKET  57
+#endif
+
+#ifndef MAX_IIO_STACK
+#define MAX_IIO_STACK             12
+#endif
+
+#define MAX_LOGIC_IIO_STACK       14
+
+#define MAX_COMPUTE_DIE           1
+#define MAX_CHA_MAP               (2 * MAX_COMPUTE_DIE)  //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
+
+#pragma pack(1)
+
+typedef struct _UINT64_STRUCT {
+  UINT32  lo;
+  UINT32  hi;
+} UINT64_STRUCT, *PUINT64_STRUCT;
+
+#ifndef MMIO_BARS_ENUM
+#define MMIO_BARS_ENUM
+typedef enum {
+  TYPE_SCF_BAR = 0,
+  TYPE_PCU_BAR,
+  TYPE_MEM_BAR0,
+  TYPE_MEM_BAR1,
+  TYPE_MEM_BAR2,
+  TYPE_MEM_BAR3,
+  TYPE_MEM_BAR4,
+  TYPE_MEM_BAR5,
+  TYPE_MEM_BAR6,
+  TYPE_MEM_BAR7,
+  TYPE_SBREG_BAR,
+  TYPE_MAX_MMIO_BAR
+} MMIO_BARS;
+#endif
+
+typedef struct {
+    UINT8       Device;
+    UINT8       Function;
+} IIO_PORT_INFO;
+
+typedef struct {
+  UINT8   Major;
+  UINT8   Minor;
+  UINT8   Revision;
+  UINT16  BuildNumber;
+} RC_VERSION;
+
+//--------------------------------------------------------------------------------------//
+// Structure definitions for Universal Data Store (UDS)
+//--------------------------------------------------------------------------------------//
+typedef struct {
+  UINT8                     Valid;         // TRUE, if the link is valid (i.e reached normal operation)
+  UINT8                     PeerSocId;     // Socket ID
+  UINT8                     PeerSocType;   // Socket Type (0 - CPU; 1 - IIO)
+  UINT8                     PeerPort;      // Port of the peer socket
+} QPI_PEER_DATA;
+
+typedef struct {
+  UINT8                     Valid;
+  UINT32                    MmioBar[TYPE_MAX_MMIO_BAR];
+  UINT8                     PcieSegment;
+  UINT64_STRUCT             SegMmcfgBase;
+  UINT32                    StackPresentBitmap;
+  UINT16                    CxlPresentBitmap;
+  UINT16                    Cxl20CapableBitmap;
+  UINT8                     TotM3Kti;
+  UINT8                     TotCha;
+  UINT32                    ChaList[MAX_CHA_MAP];
+  UINT32                    SocId;
+  QPI_PEER_DATA             PeerInfo[MAX_FW_KTI_PORTS];    // QPI LEP info
+} QPI_CPU_DATA;
+
+typedef struct {
+  UINT8                     Valid;
+  UINT8                     SocId;
+  QPI_PEER_DATA             PeerInfo[MAX_SOCKET];    // QPI LEP info
+} QPI_IIO_DATA;
+
+typedef struct {
+    IIO_PORT_INFO           PortInfo[MAX_IIO_PORTS_PER_SOCKET];
+} IIO_DMI_PCIE_INFO;
+
+typedef struct _STACK_RES {
+  UINT8                   Personality;
+  UINT8                   BusBase;               // Base of Bus configured for this stack
+  UINT8                   BusLimit;              // Limit of Bus configured for this stack
+  UINT16                  IoBase;                // Base of IO configured for this stack
+  UINT16                  IoLimit;               // Limit of IO configured for this stack
+  UINT32                  IoApicBase;
+  UINT32                  IoApicLimit;
+  UINT32                  Mmio32Base;            // Base of low MMIO configured for this stack in memory map
+  UINT32                  Mmio32Limit;           // Limit of low MMIO configured for this stack in memory map
+  UINT64                  Mmio64Base;            // Base of high MMIO configured for this stack in memory map
+  UINT64                  Mmio64Limit;           // Limit of high MMIO configured for this stack in memory map
+  UINT8                   PciResourceBusBase;    // Base of Bus resource available for PCI devices
+  UINT8                   PciResourceBusLimit;   // Limit of Bus resource available for PCI devices
+  UINT16                  PciResourceIoBase;     // Base of IO resource available for PCI devices
+  UINT16                  PciResourceIoLimit;    // Limit of IO resource available for PCI devices
+  UINT32                  PciResourceMem32Base;  // Base of low MMIO resource available for PCI devices
+  UINT32                  PciResourceMem32Limit; // Limit of low MMIO resource available for PCI devices
+  UINT64                  PciResourceMem64Base;  // Base of high MMIO resource available for PCI devices
+  UINT64                  PciResourceMem64Limit; // Limit of high MMIO resource available for PCI devices
+  UINT32                  VtdBarAddress;         // NOTE: Obsolete, not used in next gen platforms
+} STACK_RES;
+
+typedef struct {
+    UINT8                   Valid;
+    UINT8                   SocketID;            // Socket ID of the IIO (0..3)
+    UINT8                   BusBase;
+    UINT8                   BusLimit;
+    UINT16                  PciResourceIoBase;
+    UINT16                  PciResourceIoLimit;
+    UINT32                  IoApicBase;
+    UINT32                  IoApicLimit;
+    UINT32                  Mmio32Base;          // Base of low MMIO configured for this socket in memory map
+    UINT32                  Mmio32Limit;         // Limit of low MMIO configured for this socket in memory map
+    UINT64                  Mmio64Base;          // Base of high MMIO configured for this socket in memory map
+    UINT64                  Mmio64Limit;         // Limit of high MMIO configured for this socket in memory map
+    STACK_RES               StackRes[MAX_LOGIC_IIO_STACK];
+    IIO_DMI_PCIE_INFO       PcieInfo;            // NOTE: Obsolete, not used in next gen platforms
+} IIO_RESOURCE_INSTANCE;
+
+typedef struct {
+    UINT16                  PlatGlobalIoBase;       // Global IO Base
+    UINT16                  PlatGlobalIoLimit;      // Global IO Limit
+    UINT32                  PlatGlobalMmio32Base;   // Global Mmiol base
+    UINT32                  PlatGlobalMmio32Limit;  // Global Mmiol limit
+    UINT64                  PlatGlobalMmio64Base;   // Global Mmioh Base [43:0]
+    UINT64                  PlatGlobalMmio64Limit;  // Global Mmioh Limit [43:0]
+    QPI_CPU_DATA            CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
+    QPI_IIO_DATA            IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
+    UINT32                  MemTsegSize;
+    UINT64                  PciExpressBase;
+    UINT32                  PciExpressSize;
+    UINT32                  MemTolm;
+    IIO_RESOURCE_INSTANCE   IIO_resource[MAX_SOCKET];
+    UINT8                   numofIIO;
+    UINT8                   MaxBusNumber;
+    UINT32                  packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
+    UINT8                   EVMode;
+    UINT8                   SkuPersonality[MAX_SOCKET];
+    UINT16                  IoGranularity;
+    UINT32                  MmiolGranularity;
+    UINT64_STRUCT           MmiohGranularity;
+    UINT8                   RemoteRequestThreshold;  //5370389
+    UINT32                  UboxMmioSize;
+    UINT32                  MaxAddressBits;
+} PLATFORM_DATA;
+
+typedef struct {
+    UINT8                   CurrentUpiiLinkSpeed;// Current programmed UPI Link speed (Slow/Full speed mode)
+    UINT8                   CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT)
+    UINT8                   OutKtiCpuSktHotPlugEn;            // 0 - Disabled, 1 - Enabled for PM X2APIC
+    UINT32                  OutKtiPerLinkL1En[MAX_SOCKET];    // output kti link enabled status for PM
+    UINT8                   IsocEnable;
+    UINT32                  meRequestedSize; // Size of the memory range requested by ME FW, in MB
+    UINT8                   DmiVc1;
+    UINT8                   DmiVcm;
+    UINT32                  CpuPCPSInfo;
+    UINT8                   cpuSubType;
+    UINT8                   SystemRasType;
+    UINT8                   numCpus;                                        // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
+    UINT16                  tolmLimit;
+    RC_VERSION              RcVersion;
+    BOOLEAN                 MsrTraceEnable;
+    UINT8                   DdrXoverMode;           // DDR 2.2 Mode
+    // For RAS
+    UINT8                   bootMode;
+    UINT8                   OutClusterOnDieEn; // Whether RC enabled COD support
+    UINT8                   OutSncEn;
+    UINT8                   OutNumOfCluster;
+    UINT8                   imcEnabled[MAX_SOCKET][MAX_IMC];
+    UINT16                  LlcSizeReg;
+    UINT8                   chEnabled[MAX_SOCKET][MAX_CH];
+    UINT8                   memNode[MC_MAX_NODE];
+    UINT8                   IoDcMode;
+    UINT8                   DfxRstCplBitsEn;
+    UINT8                   BitsUsed;    //For 5 Level Paging
+} SYSTEM_STATUS;
+
+typedef struct {
+    PLATFORM_DATA           PlatformData;
+    SYSTEM_STATUS           SystemStatus;
+    UINT32                  OemValue;
+} IIO_UDS;
+#pragma pack()
+
+#endif  //#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h
new file mode 100644
index 0000000..2534f9a
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h
@@ -0,0 +1,371 @@
+/** @file
+  GUID used for Memory Map Data entries in the HOB list.
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 1999 - 2022 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _MEMORY_MAP_DATA_HOB_H_
+#define _MEMORY_MAP_DATA_HOB_H_
+
+#define MEMORY_MAP_HOB_GUID \
+  { \
+    0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \
+  }
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET                       4
+#endif
+
+#ifndef MAX_IMC
+#define MAX_IMC                          4                     // Maximum memory controllers per socket
+#endif
+
+#ifndef MAX_MC_CH
+#define MAX_MC_CH                        2                     // Max number of channels per MC (3 for EP)
+#endif
+
+#ifndef MAX_CH
+#define MAX_CH                           ((MAX_IMC)*(MAX_MC_CH))     // Max channels per socket (worst case EP * EX combination = 16)
+#endif
+
+#define MAX_CXL_AMT                       0
+
+#ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE
+#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE    2                         // Max number of unique interleaves for NGN DIMM
+#endif
+
+#ifndef MAX_SPARE_RANK
+#define MAX_SPARE_RANK                    2             // Max number of spare ranks in a channel
+#endif
+
+#ifndef MAX_HBM_IO
+#define MAX_HBM_IO                        4
+#endif
+
+#ifndef MAX_DIMM
+#define MAX_DIMM                          2                       // Max DIMM per channel
+#endif
+
+#ifndef MAX_RANK_DIMM
+#define MAX_RANK_DIMM                     2
+#endif
+
+#ifndef MAX_DRAM_CLUSTERS
+#define MAX_DRAM_CLUSTERS                 4
+#endif
+
+#ifndef MAX_SAD_RULES
+#define MAX_SAD_RULES                     16
+#endif
+
+#ifndef MAX_FPGA_REMOTE_SAD_RULES
+#define MAX_FPGA_REMOTE_SAD_RULES         2     // Maximum FPGA sockets exists on ICX platform
+#endif
+
+#define MAX_SI_SOCKET                     8   // Maximum silicon supported socket number
+
+#define MAX_AMT                           (MAX_IMC+MAX_CXL_AMT)      // Max abstract memory target per socket
+#define AMT_MAX_NODE                      ((MAX_AMT)*(MAX_SOCKET))   // Max abstract memory target for all sockets
+
+// NGN
+#define NGN_MAX_SERIALNUMBER_STRLEN       4
+#define NGN_MAX_PARTNUMBER_STRLEN         30
+#define NGN_FW_VER_LEN                    4
+#define NGN_LOG_TYPE_NUM                  2
+#define NGN_LOG_LEVEL_NUM                 2
+
+/**
+ * Memory channel index conversion macros.
+ *
+ * We got two types of memory channel indexes:
+ * - socket channel - indexes 0..MAX_CH, used in [socket][channel] indexing
+ * - IMC channel    - indexes 0..MAX_MC_CH, used in [socket][IMC][channel] indexing
+ * The below defined macros convert one channel index to the other one.
+ */
+#define MEM_SKTCH_TO_IMC(SktCh)     ((SktCh) / MAX_MC_CH)
+#define MEM_SKTCH_TO_IMCCH(SktCh)   ((SktCh) % MAX_MC_CH)
+#define MEM_IMCCH_TO_SKTCH(Imc, Ch) ((Imc) * MAX_MC_CH + (Ch))
+
+#define MEM_64MB_TO_BYTES(Size64M)  ((UINT64)(Size64M) << 26)
+#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16)
+#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6)
+#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4)
+#define MEM_BYTES_TO_64MB(SizeB)    ((SizeB) >> 26)
+#define MEM_KBYTES_TO_64MB(SizeKB)  ((SizeKB) >> 16)
+#define MEM_MBYTES_TO_64MB(SizeMB)  ((SizeMB) >> 6)
+
+typedef UINT8               CXL_INTLV_SET_KEY;
+
+#define FSP_RESERVED1_LEN                 77
+#define FSP_RESERVED2_LEN                 2174
+#define FSP_RESERVED3_LEN                 21
+#define FSP_RESERVED4_LEN                 130
+#define FSP_RESERVED5_LEN                 10
+#define FSP_RESERVED6_LEN                 800
+#pragma pack(1)
+
+typedef enum {
+  DIMM_RANK_MAP_OUT_UNKNOWN = 0,
+  DIMM_RANK_MAP_OUT_MEM_DECODE,
+  DIMM_RANK_MAP_OUT_POP_POR_VIOLATION,
+  DIMM_RANK_MAP_OUT_RANK_DISABLED,
+  DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE,
+  DIMM_RANK_MAP_OUT_MAX
+} DIMM_RANK_MAP_OUT_REASON;
+
+struct RankDevice {
+  UINT8   enabled;                // 0 = disabled,  1 = enabled
+  UINT8   logicalRank;            // Logical Rank number (0 - 7)
+  UINT16  rankSize;               // Units of 64 MB
+};
+
+struct PersisentDpaMap
+{
+    UINT32 perRegionDPAOffset;
+    UINT32 SPALimit;
+};
+
+typedef struct firmwareRev {
+  UINT8  majorVersion;
+  UINT8  minorVersion;
+  UINT8  hotfixVersion;
+  UINT16 buildVersion;
+} FIRMWARE_REV;
+
+typedef struct DimmDevice {
+  UINT8                     Present;
+  BOOLEAN                   Enabled;
+  UINT8                     DcpmmPresent;                                 // 1 - This is a DCPMM
+  UINT8                     X4Present;
+  UINT8                     DramIoWidth;                                  // Actual DRAM IO Width (4, 8, 16)
+  UINT8                     NumRanks;
+  UINT8                     keyByte;
+  UINT8                     actKeyByte2;                                  // Actual module type reported by SPD
+  UINT8                     actSPDModuleOrg;                              // Actual number of DRAM ranks and device width
+  UINT8                     dimmTs;                                       // Thermal sensor data.
+  UINT16                    VolCap;                                       // Volatile capacity (AEP DIMM only)
+  UINT16                    nonVolCap;                                    // Non-volatile capacity (AEP DIMM only)
+  UINT16                    DimmSize;
+  UINT32                    NVmemSize;
+  UINT16                    SPDMMfgId;                                    // Module Mfg Id from SPD
+  UINT16                    VendorID;
+  UINT16                    DeviceID;
+  UINT16                    RevisionID;
+  UINT32                    perRegionDPA;                                 // DPA of PMEM that Nfit needs
+  struct  PersisentDpaMap   perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE];    // DPA map
+  UINT8                     serialNumber[NGN_MAX_SERIALNUMBER_STRLEN];    // Serial Number
+  UINT8                     PartNumber[NGN_MAX_PARTNUMBER_STRLEN];        // Part Number
+  UINT8                     FirmwareVersionStr[NGN_FW_VER_LEN];           // Used to update the SMBIOS TYPE 17
+  struct  firmwareRev       FirmwareVersion;                              // Firmware revision
+  struct  RankDevice        rankList[MAX_RANK_DIMM];
+  UINT16                    InterfaceFormatCode;
+  UINT16                    SubsystemVendorID;
+  UINT16                    SubsystemDeviceID;
+  UINT16                    SubsystemRevisionID;
+  UINT16                    FisVersion;                                   // Firmware Interface Specification version
+  UINT8                     DimmSku;                                      // Dimm SKU info
+  UINT8                     manufacturingLocation;                        // Manufacturing location for the NVDIMM
+  UINT16                    manufacturingDate;                            // Date the NVDIMM was manufactured
+  INT32                     commonTck;
+  UINT8                     EnergyType;                                   // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
+  BOOLEAN                   NvDimmNPresent;                               // JEDEC NVDIMM-N Type Memory Present
+  UINT8                     CidBitMap;                                    // SubRankPer CS for DIMM device
+  UINT16                    SPDRegVen;                                    // Register Vendor ID in SPD
+  DIMM_RANK_MAP_OUT_REASON  MapOutReason;
+} MEMMAP_DIMM_DEVICE_INFO_STRUCT;
+
+struct ChannelDevice {
+  UINT8                               Enabled;                            // 0 = channel disabled, 1 = channel enabled
+  UINT8                               Features;                           // Bit mask of features to enable or disable
+  UINT8                               MaxDimm;                            // Number of DIMM
+  UINT8                               NumRanks;                           // Number of ranks on this channel
+  UINT8                               chFailed;
+  UINT8                               ngnChFailed;
+  UINT8                               Is9x4DimmPresent;                   // 9x4 dimm present indicator
+  UINT8                               SpareLogicalRank[MAX_SPARE_RANK];   // Logical rank, selected as Spare
+  UINT8                               SparePhysicalRank[MAX_SPARE_RANK];  // Physical rank, selected as spare
+  UINT16                              SpareRankSize[MAX_SPARE_RANK];      // spare rank size
+  UINT8                               EnabledLogicalRanks;                // Bitmap of Logical ranks that are enabled
+  UINT8                               DdrPopulationMap;                   // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+  UINT8                               PmemPopulationMap;                  // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+  MEMMAP_DIMM_DEVICE_INFO_STRUCT      DimmInfo[MAX_DIMM];
+};
+
+struct memcontroller {
+  UINT32    MemSize;
+};
+
+typedef enum {
+  MemTypeNone = 0,
+  MemType1lmDdr,
+  MemType1lmAppDirect,
+  MemType1lmAppDirectReserved,
+  MemType1lmCtrl,
+  MemType1lmHbm,
+  MemTypeNxm,
+  MemType2lmDdrCacheMemoryMode,
+  MemType2lmDdrWbCacheAppDirect,
+  MemType2lmHbmCacheDdr,
+  MemType2lmHbmCacheMemoryMode,
+  MemTypeCxlAccVolatileMem,
+  MemTypeCxlAccPersistentMem,
+  MemTypeFpga,
+  MemTypeCxlExpVolatileMem,
+  MemTypeCxlExpPersistentMem,
+  MemTypeCxl2lmDdrCacheMem,
+  MemTypeCxlHetero,
+  MemTypeMax
+} MEM_TYPE;
+
+typedef struct SADTable {
+  UINT8    Enable;         // Rule enable
+  MEM_TYPE type;           // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges.
+  UINT8    granularity;    // Interleave granularities for current SAD entry.  Possible interleave granularity options depend on the SAD entry type.  Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
+  UINT32   Base;           // Base of the current SAD entry
+  UINT32   Limit;          // Limit of the current SAD entry
+  UINT8    ways;           // Interleave ways for SAD
+  UINT8    channelInterBitmap[MAX_AMT];   //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+  UINT8    FMchannelInterBitmap[MAX_AMT];   //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+  UINT8    NmChWays;         // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM.
+  UINT8    FmChWays;         // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT.
+  UINT16   imcInterBitmap;   // Bit map to denote which IMCs are interleaved from this socket.
+  UINT16   NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
+  BOOLEAN  local;          // 0 - Remote 1- Local
+  UINT8    IotEnabled;     // To indicate if IOT is enabled
+  UINT8    mirrored;       // To Indicate the SAD is mirrored while enabling partial mirroring
+  UINT8    Attr;
+  UINT8    tgtGranularity; // Interleave mode for target list
+  UINT8    Cluster;        // SNC cluster, hemisphere, or quadrant index.
+  UINT8    HostBridgeGran; // Host bridge interleaving granularity.
+  UINT32   HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD.
+  CXL_INTLV_SET_KEY   CxlIntlvSetKey;   // The unique key of CXL interleave set. (7nm)
+} SAD_TABLE;
+
+typedef struct socket {
+  UINT8      SocketEnabled;
+  UINT32     IioStackBitmap;
+  BOOLEAN    HbmIoEn[MAX_HBM_IO];                    // Flag indicates if HBM IO is enabled. TRUE: HBM IO is Enabled, FALSE: HBM IO is disabled.
+  UINT8      imcEnabled[MAX_IMC];
+  UINT8      SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list
+  UINT32     SktTotMemMapSPA;                        // Total memory mapped to SPA
+  UINT32     SktMemSize2LM;                          // Total memory excluded from Limit
+  SAD_TABLE  SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES];                     // SAD table
+  struct     memcontroller imc[MAX_IMC];
+  struct     ChannelDevice ChannelInfo[MAX_CH];
+} MEMMAP_SOCKET;
+
+typedef struct {
+  UINT8  Enabled;           // Indicates if this EDC is enabled
+  UINT32 MemAsCache;        // Memory used as Cache, in 64MB units
+  UINT32 MemAsFlat;         // Memory used as Flat memory, in 64MB units
+} EDC_INFO;
+
+typedef struct SystemMemoryMapElement {
+  UINT16   Type;           // Type of this memory element; Bit0: 1LM  Bit1: 2LM  Bit2: PMEM  Bit3: PMEM-cache  Bit4: BLK Window  Bit5: CSR/Mailbox/Ctrl region
+  UINT8    NodeId;         // Node ID of the HA Owning the memory
+  UINT8    SocketId;       // Socket Id of socket that has his memory - ONLY IN NUMA
+  UINT8    SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
+  UINT16   ImcInterBitmap; // IMC interleave bitmap for this memory
+  UINT8    ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+  UINT32   BaseAddress;    // Base Address of the element in 64MB chunks
+  UINT32   ElementSize;    // Size of this memory element in 64MB chunks
+} SYSTEM_MEMORY_MAP_ELEMENT;
+
+typedef struct SystemMemoryMapHob {
+  //
+  // Total Clusters. In SNC2 mode there are 2 clusters and SNC4 mode has 4 clusters.
+  // All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1).
+  //
+  UINT8    TotalClusters;
+
+  UINT8    reserved1[FSP_RESERVED1_LEN];          // MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure
+  UINT32   lowMemBase;                            // Mem base in 64MB units for below 4GB mem.
+  UINT32   lowMemSize;                            // Mem size in 64MB units for below 4GB mem.
+  UINT32   highMemBase;                           // Mem base in 64MB units for above 4GB mem.
+  UINT32   highMemSize;                           // Mem size in 64MB units for above 4GB mem.
+  UINT32   memSize;                               // Total physical memory size
+  UINT16   memFreq;                               // Mem Frequency
+  UINT16   HbmFreq;                               // HBM Frequency in MHz.
+  UINT8    memMode;                               // 0 - Independent, 1 - Lockstep
+  UINT8    volMemMode;                            // 0 - 1LM, 1 - 2LM
+  UINT8    CacheMemType;                          // 0 - DDR$DDRT, 1 - HBM$DDR. Only valid if volMemMode is 2LM
+  UINT16   DramType;
+  UINT8    DdrVoltage;
+  BOOLEAN  SupportedPMemPresent;                  // TRUE if at least one PMem is present and supported by BIOS
+  BOOLEAN  EkvPresent;                            // Set if EKV controller on system
+  BOOLEAN  BwvPresent;                            // Set if BWV controller on system
+  BOOLEAN  CwvPresent;                            // Set if CWV controller on system
+  UINT8    XMPProfilesSup;
+  UINT8    XMPCapability;
+  //
+  // HBM Specific Info.
+  //
+  UINT16   HbmInstances[MAX_SOCKET];              // Total HBM instances
+  UINT32   HbmFlatMemSize;                        // Total HBM memory size in 64MB units, if HBM used as Flat memory
+  UINT32   HbmCacheMemSize;                       // Total HBM memory used as cache, if HBM used as Cache memory
+  UINT16   HbmSpeed;                              // Configured HBM (i.e OPIO channel) speed in MT/s.
+  UINT16   MaxHbmSpeed;                           // Max HBM (i.e OPIO channel) speed in MT/s.
+  UINT8    SystemRasType;
+  UINT8    RasModesEnabled;                       // RAS modes that are enabled
+  UINT16   ExRasModesEnabled;                     // Extended RAS modes that are enabled
+  UINT8    sncEnabled;                            // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
+  UINT8    NumOfCluster;
+  UINT8    NumChPerMC;
+  UINT8    numberEntries;                         // Number of Memory Map Elements
+  SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
+  UINT8   reserved2[FSP_RESERVED2_LEN];                // struct   memSetup MemSetup;
+  UINT8   reserved3[FSP_RESERVED3_LEN];                // MEM_DFXMEMVARS    DfxMemVar;
+  MEMMAP_SOCKET Socket[MAX_SOCKET];
+  UINT8   reserved4[FSP_RESERVED4_LEN];                // struct   memTiming  profileMemTime[XMP_MAX_PROFILES];
+
+  UINT8   reserved5[FSP_RESERVED5_LEN];                // RASMEMORYINFO  RasMeminfo;
+  UINT8   LatchSystemShutdownState;
+  BOOLEAN IsWpqFlushSupported;
+  UINT8   EadrSupport;
+  UINT8   EadrCacheFlushMode;
+  UINT8   SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH];  //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH
+  UINT8   reserved6[FSP_RESERVED6_LEN];                // HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH];
+  UINT32  DdrCacheSize[MAX_SOCKET][MAX_CH];            // Size of DDR memory reserved for 2LM cache (64MB granularity)
+  BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH];   // ADR state for Intel PMEM Modules
+  UINT16  BiosFisVersion;                              // Firmware Interface Specification version currently supported by BIOS
+  UINT16  MaxAveragePowerLimit;                        // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW)
+  UINT16  MinAveragePowerLimit;                        // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW)
+  UINT16  CurrAveragePowerLimit;                       // Current Power limit in mW used for average power
+  UINT16  MaxMbbPowerLimit;                            // Max MBB power limit ( Valid range ends at 18000mW).
+  UINT16  MinMbbPowerLimit;                            // Min MBB power limit ( Valid range starts from 15000mW).
+  UINT16  CurrMbbPowerLimit;                           // Current Power limit in mW used for MBB power
+  UINT32  MaxMbbAveragePowerTimeConstant;              // Max MBB Average Power Time Constant
+  UINT32  MinMbbAveragePowerTimeConstant;              // Min MBB Average Power Time Constant
+  UINT32  CurrMbbAveragePowerTimeConstant;             // Current MBB Average Power Time Constant
+  UINT32  MmiohBase;                                   // MMIOH base in 64MB granularity
+  UINT8   MaxSadRules;                                 // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon)
+  UINT8   NumberofChaDramClusters;                     // Number of CHA DRAM decoder clusters
+  BOOLEAN VirtualNumaEnable;                           // Enable or Disable Virtual NUMA
+  UINT8   VirtualNumOfCluster;                         // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster)
+} SYSTEM_MEMORY_MAP_HOB;
+
+#pragma pack()
+
+#endif // _MEMORY_MAP_DATA_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h
new file mode 100644
index 0000000..8df3e85
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h
@@ -0,0 +1,82 @@
+/** @file
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 2007 -2021  Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _PREV_BOOT_ERR_SRC_HOB_H_
+#define _PREV_BOOT_ERR_SRC_HOB_H_
+
+#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID \
+{ 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 }
+
+#define PREV_BOOT_ERR_SRC_HOB_SIZE  1000
+
+#pragma pack(1)
+
+typedef struct {
+UINT16  Length;    // Actual size of the error sources  used in the HOB
+UINT8  HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2];  // List of Error source structures of format //MCBANK_ERR_INFO  or CSR_ERR_INFO
+}PREV_BOOT_ERR_SRC_HOB;
+
+typedef struct{
+UINT8  Type;    // McBankType = 1;
+UINT8  Segment;
+UINT8  Socket;
+UINT16  ApicId;    // ApicId  is Needed only if it a core McBank.
+UINT16  McBankNum;
+UINT64  McBankStatus;
+UINT64  McbankAddr;
+UINT64  McBankMisc;
+} MCBANK_ERR_INFO;
+
+typedef struct {
+UINT8  Type;    // PciExType =2 ;
+UINT8  Segment;
+UINT8  Bus;
+UINT8  Device;
+UINT8  Function;
+UINT32  AerUncErrSts;
+UINT8  AerHdrLogData[16];
+} PCI_EX_ERR_INFO;
+
+typedef struct {
+UINT8  Type;    // Other Csr error type =3 ;
+UINT8  Segment;
+UINT8  Bus;
+UINT8  Device;
+UINT8  Function;
+UINT16  offset;
+UINT32  Value;
+} CSR_ERR_INFO;
+
+typedef enum {
+  McBankType = 1,
+  PciExType,
+  CsrOtherType
+} ERROR_ACCESS_TYPE;
+
+#pragma pack()
+
+#endif //_PREV_BOOT_ERR_SRC_HOB_H_
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h
new file mode 100644
index 0000000..e87c6e9
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h
@@ -0,0 +1,281 @@
+/** @file
+  System Information HOB Hearder File
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 2017 - 2021 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _SYSTEM_INFO_HOB_H_
+#define _SYSTEM_INFO_HOB_H_
+
+#define SYSTEM_INFO_HOB_GUID          { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }}
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET                    4
+#endif
+
+#ifndef MAX_IIO_STACK
+#define MAX_IIO_STACK                 12
+#endif
+
+#define MAX_LOGIC_IIO_STACK           14
+
+#ifndef MAX_IMC
+#define MAX_IMC                       4                     // Maximum memory controllers per socket
+#endif
+
+#ifndef MAX_MC_CH
+#define MAX_MC_CH                     2                     // Max number of channels per MC (3 for EP)
+#endif
+
+#ifndef MAX_CH
+#define MAX_CH                        ((MAX_IMC)*(MAX_MC_CH))     // Max channels per socket (worst case EP * EX combination = 16)
+#endif
+
+#define MAX_HPM_PFS_ENTRY_NUM         15      // Number of entries in PFS structure
+#define HPM_PFS_ENTRY_SIZE            2       // Entry size of PFS structure in DWORD
+
+#pragma pack(1)
+
+#ifndef MMIO_BARS_ENUM
+#define MMIO_BARS_ENUM
+typedef enum {
+  TYPE_SCF_BAR = 0,
+  TYPE_PCU_BAR,
+  TYPE_MEM_BAR0,
+  TYPE_MEM_BAR1,
+  TYPE_MEM_BAR2,
+  TYPE_MEM_BAR3,
+  TYPE_MEM_BAR4,
+  TYPE_MEM_BAR5,
+  TYPE_MEM_BAR6,
+  TYPE_MEM_BAR7,
+  TYPE_SBREG_BAR,
+  TYPE_MAX_MMIO_BAR
+} MMIO_BARS;
+#endif
+
+typedef enum {
+  ReservedMemSs,
+  Ddr4MemSs = 1,
+  Ddr5MemSs = 2,
+  LpDdr4MemSs = 3,
+  LpDdr5MemSs = 4,
+  Hbm2MemSs = 5,
+  MrcMstMax,
+  MrcMstDelim = MAX_INT32
+} MRC_MST;
+
+typedef enum BootMode {
+  NormalBoot  = 0,  // Normal path through RC with full init, mem detection, init, training, etc.
+                    //    Some of these MRC specific init routines can be skipped based on MRC input params
+                    //    in addition to the sub-boot type (WarmBoot, WarmBootFast, etc).
+  S3Resume    = 1   // S3 flow through RC. Should do the bare minimum required for S3
+                    //    init and be optimized for speed.
+} BootMode;
+
+//
+// This is used to determine what type of die is connected to a UPI link
+//
+typedef enum {
+  UpiConnectionTypeCpu,
+  UpiConnectionTypePcieGen4,
+  UpiConnectionTypeFpga,
+  UpiConnectionTypeMax
+} UPI_CONNECTION_TYPE;
+
+//
+// VSEC info for HPM
+// The HPM_INFO struct contains info collected from the VSEC structure for the HPM.
+// VSEC Structure is defined as below:
+//
+// ------------------------VSEC Structure------------------------
+// | Next Cap Offset(12b)  | Cap Version(4b) | PCIe Cap ID(16b) |
+// --------------------------------------------------------------
+// |     VSEC_LEN(12b)     |   VSEC_REV(4b)  |   VSEC_ID(16b)   |
+// --------------------------------------------------------------
+// | EntrySize(8b)     |     NumEntries(8b)  |    Rsvd(16b)     |
+// --------------------------------------------------------------
+// |                 Address(29b)                    | tBIR(3b) |
+// --------------------------------------------------------------
+//
+//
+typedef struct {
+  UINT8        NumEntries;  // The number of PM feature interface instances in this VSEC space
+  UINT8        EntrySize;   // The entry size for each PM interface instance in 32-bit DWORDs
+  UINT32       Address;     // The offset from the BAR register which is used for HPM to point to the base of the discovery entry. i.e. the PFS (PM Feature Structure)
+  UINT8        tBIR;        // Which one of he function's BAR is used for the PFS offset
+} HPM_INFO;
+
+//
+//-------------------------------- - PFS Entry--------------------------------
+//|  EntrySize(16b)                     |  NumEntries(8b)  |  VSEC_SubID(8b)  |
+//----------------------------------------------------------------------------
+//| RSVD(14b)                | Attr(2b) |       CapOffset(16b)                |
+//----------------------------------------------------------------------------
+//
+typedef struct {
+  UINT32                TpmiId : 8;
+  UINT32                NumEntries : 8;
+  UINT32                EntrySize : 16;
+  UINT32                CapOffset : 16;
+  UINT32                Attribute : 2;
+  UINT32                EntryBitMap : 8;
+  UINT32                Rsvd : 6;
+} PFS_ENTRY;
+
+//
+// HPM (Hierarchical Power Management) VSEC resource allocation info
+//
+typedef struct {
+  BOOLEAN             HpmEnabled;                   // HPM enabled or not in BIOS knob
+  BOOLEAN             HpmInfraReady;                // All the HPM infrastructure data is buffered
+  UINT32              OobMsmHpmBarBase;               // The base of OOBMSM BAR1 for HPM PFS and LUT tables
+  UINT32              OobMsmHpmBarLimit;              // The limit of OOBMSM BAR1 from where the required size will be allocated
+  UINT32              OobMsmHpmBarMmcfgAddress;       // The OOBMSM BAR1 MMCFG address
+  UINT32              OobMsmHpmBarRequiredSize;       // The required size of OOBMSM BAR1
+
+  HPM_INFO            HpmVsecInfo;                  // For now, single VSEC is assumed
+  PFS_ENTRY           Pfs[MAX_HPM_PFS_ENTRY_NUM];   // The buffered PFS structure
+
+} HPM_VSEC_RESOURCE;
+
+//
+// Stack id swap information, which includes stack swap flag and the new stack id swap array.
+//
+typedef struct {
+  BOOLEAN StackSwapFlag;
+  UINT8   StackIdSwapArray[MAX_IIO_STACK];
+} STACKID_SWAP_INFO;
+
+typedef struct {
+  UINT64  Cxl1p1RcrbBase;
+  BOOLEAN Cxl1p1RcrbValid;
+} CXL_1P1_RCRB;
+
+typedef struct {
+  UINT32 StackPresentBitmap[MAX_SOCKET];           ///< bitmap of present stacks per socket
+  UINT8  StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack
+  UINT32 StackMmiol[MAX_SOCKET][MAX_IIO_STACK];    ///< mmiol of each IIO stack, if it works as CXL, the mmiol base is RCRBBAR
+  UINT8  SocketFirstBus[MAX_SOCKET];
+  UINT8  Socket10nmUboxBus0[MAX_SOCKET];           //10nm CPU use only
+  UINT8  TotIoDie[MAX_SOCKET];                     //GNR & SRF CPU use only
+  UINT8  TotCmpDie[MAX_SOCKET];                    //GNR & SRF CPU use only
+  UINT8  SocketLastBus[MAX_SOCKET];
+  UINT8  segmentSocket[MAX_SOCKET];
+  UINT8  KtiPortCnt;
+  UINT32 socketPresentBitMap;
+  UINT32 SecondaryNodeBitMap;
+  UINT32 FpgaPresentBitMap;
+  UINT32 mmCfgBase;
+  UINT64 SocketMmCfgBase[MAX_SOCKET];
+  UINT8  DdrMaxCh;
+  UINT8  DdrMaxImc;                               ///< Logical number of IMC count, ignoring logical holes
+  UINT8  DdrPhysicalMaxImc;                       ///< Physical number of IMC count from Capid
+  UINT8  DdrNumChPerMc;
+  UINT8  DdrNumPseudoChPerCh;
+  UINT8  imcEnabled[MAX_SOCKET][MAX_IMC];
+  UINT8  mcId[MAX_SOCKET][MAX_CH];
+  MRC_MST MemSsType[MAX_SOCKET];                    ///< MemSsType global identifier for DDR vs. HBM
+  UINT32  MmioBar[MAX_SOCKET][TYPE_MAX_MMIO_BAR];
+  UINT8   HbmMaxCh;
+  UINT8   HbmMaxIoInst;
+  UINT8   HbmNumChPerMc;
+  UINT8   HbmNumChPerIo;
+  UINT32  LastCsrAddress[2];
+  UINT32  LastCsrMmioAddr;
+  UINT8   CsrCachingEnable;
+  UINT32  LastCsrMcAddress[2];
+  UINT32  LastCsrMcMmioPhyAddr;
+  UINT8   CsrPciBarCachingEnable;
+  UINT32  LastCsrPciBarAddr[2];
+  UINT64  LastCsrPciBarPhyAddr;
+  UINT32  LastSBPortId[MAX_SOCKET];
+  UPI_CONNECTION_TYPE         UpiConnectionType[MAX_SOCKET];
+  BOOLEAN PostedCsrAccessAllowed;                   // SW is allowed to use posted CSR writes method when TRUE
+  BOOLEAN PostedWritesEnabled;                      // All CSR writes use posted method when TRUE, non-posted when FALSE
+  BOOLEAN DataPopulated;                            // CPU_CSR_ACCESS_VAR is unavailable when FALSE
+  HPM_VSEC_RESOURCE SocketHpmVsecRes[MAX_SOCKET];   // HPM VSEC info for all sockets
+  BOOLEAN HbmSku;
+  UINT8   HcxType[MAX_SOCKET];
+  STACKID_SWAP_INFO StackIdSwapInfo[MAX_SOCKET];    //StackID sync after do StackId swap,including Stack swap table and whether do stack swap
+  CXL_1P1_RCRB  Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK];    // CXL 1.1 RCRB, one per PI5 stack
+  UINT32  DmiRcrb[MAX_SOCKET];                      // DMI RCRB region, one per socket
+  UINT8   FabricType;                               //Compute die 10x6, 10x5, and 6x5 type is stored
+  UINT8   ChopType;                                 //Compute Die Chop Type
+  UINT8   MdfInstCount;
+} CPU_CSR_ACCESS_VAR;
+
+typedef struct {
+  UINT32 MeRequestedSizeNv;
+  UINT32 MeRequestedAlignmentNv;
+  UINT8  SbspSocketIdNv;
+} SYS_INFO_VAR_NVRAM;
+
+typedef struct _CPUID_REGISTER_INFO {
+  UINT32 Eax;
+  UINT32 Ebx;
+  UINT32 Ecx;
+  UINT32 Edx;
+} CPUID_REGISTER_INFO;
+
+typedef struct _PROCESSOR_COMMON_INFO {
+  UINT32  capid0;
+  UINT32  capid1;
+  UINT32  capid2;
+  UINT32  capid3;
+  UINT32  capid4;
+  UINT32  capid5;
+  UINT32  capid6lo;
+  UINT32  capid6hi;
+  CPUID_REGISTER_INFO  ExtCpuid7;
+  CPUID_REGISTER_INFO  ExtCpuid1B;
+} PROCESSOR_COMMON_INFO;
+
+typedef struct {
+  UINT32 MeRequestedSize;
+  UINT32 MeRequestedAlignment;
+  UINT32 CheckPoint;
+  UINT8  ResetRequired;
+  UINT8  Emulation;
+  BootMode SysBootMode;
+  CPU_CSR_ACCESS_VAR        CpuCsrAccessVarHost;    // Common resource for CsrAccessRoutines
+  UINT64   CpuFreq;
+  UINT8    SocketId;
+  SYS_INFO_VAR_NVRAM SysInfoVarNvram;
+  BOOLEAN  UsraTraceControl;
+  UINT16   UsraTraceConfiguration;                 // Bit               7       6        5           4                     3:0
+                                                   //               Write, Modify, GetAddr, Long/Short, Trace 0x5 as signature
+                                                   // Bit               15                              14:11   10     9     8
+                                                   // DumpCpuCsrAccessVar,                                TBD, CSR, PCIE, Read
+  BOOLEAN  CpuCsrAccessVarInfoDumped;
+  PROCESSOR_COMMON_INFO          ProcessorCommonInfo[MAX_SOCKET];
+  EFI_PHYSICAL_ADDRESS  SocAddrMapData;
+  UINTN    UsraPpiPtr;
+} SYSTEM_INFO_VAR;
+
+
+#pragma pack ()
+
+#endif //#ifndef _SYSTEM_INFO_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_cxl.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_cxl.h
new file mode 100644
index 0000000..af5ac8f
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_cxl.h
@@ -0,0 +1,41 @@
+/** @file
+
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __DEFS_CXL_H__
+#define __DEFS_CXL_H__
+
+#define CXL_SECURITY_FULLY_TRUSTED      0
+#define CXL_SECURITY_PARTIALLY_TRUSTED  1
+#define CXL_SECURITY_UNTRUSTED          2
+#define CXL_SECURITY_AUTO               3
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_iio.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_iio.h
new file mode 100644
index 0000000..7e7d9f7
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_iio.h
@@ -0,0 +1,141 @@
+/** @file
+
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __DEFS_IIO_H__
+#define __DEFS_IIO_H__
+
+#include <fsp/api.h>
+
+#define IIO_MODE_GEN4_ONLY                  0
+#define IIO_MODE_GEN5                       1
+#define IIO_MODE_CXL                        2
+#define IIO_MODE_FORCE_CXL                  3
+#define IIO_MODE_INVALID                    0xFF
+
+#define IIO_BIFURCATE_xxxxxxxx          0xFE
+#define IIO_BIFURCATE_x4x4x4x4          0x0
+#define IIO_BIFURCATE_x4x4xxx8          0x1
+#define IIO_BIFURCATE_xxx8x4x4          0x2
+#define IIO_BIFURCATE_xxx8xxx8          0x3
+#define IIO_BIFURCATE_xxxxxx16          0x4
+#define IIO_BIFURCATE_x2x2x4x8          0x5
+#define IIO_BIFURCATE_x4x2x2x8          0x6
+#define IIO_BIFURCATE_x8x2x2x4          0x7
+#define IIO_BIFURCATE_x8x4x2x2          0x8
+#define IIO_BIFURCATE_x2x2x4x4x4        0x9
+#define IIO_BIFURCATE_x4x2x2x4x4        0xA
+#define IIO_BIFURCATE_x4x4x2x2x4        0xB
+#define IIO_BIFURCATE_x4x4x4x2x2        0xC
+#define IIO_BIFURCATE_x2x2x2x2x8        0xD
+#define IIO_BIFURCATE_x8x2x2x2x2        0xE
+#define IIO_BIFURCATE_x2x2x2x2x4x4      0xF
+#define IIO_BIFURCATE_x2x2x4x2x2x4      0x10
+#define IIO_BIFURCATE_x2x2x4x4x2x2      0x11
+#define IIO_BIFURCATE_x4x2x2x2x2x4      0x12
+#define IIO_BIFURCATE_x4x2x2x4x2x2      0x13
+#define IIO_BIFURCATE_x4x4x2x2x2x2      0x14
+#define IIO_BIFURCATE_x2x2x2x2x2x2x4    0x15
+#define IIO_BIFURCATE_x2x2x2x2x4x2x2    0x16
+#define IIO_BIFURCATE_x2x2x4x2x2x2x2    0x17
+#define IIO_BIFURCATE_x4x2x2x2x2x2x2    0x18
+#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2  0x19
+#define IIO_BIFURCATE_AUTO              0xFF
+
+//------------------------------------------------------------------------------------
+// IIO IPs located in extended stacks for SPR program
+//------------------------------------------------------------------------------------
+#define HCX_BUS_RANGE             0x04
+#define HCB_BUS_RANGE             0x08
+#define CPM_BUS_OFFSET            0x01
+#define HQM_BUS_OFFSET            0x03
+#define CPM1_BUS_OFFSET           0x05
+#define HQM1_BUS_OFFSET           0x07
+#define CPM_MMIO_SIZE             0x100000000         // 4G MMIO resource for CPM
+#define HQM_MMIO_SIZE             0x400000000         // 16G MMIO resource for HQM
+#define CPM_RESERVED_BUS          0x01
+#define HQM_RESERVED_BUS          0x01
+
+#define HCT_BUS_RANGE             0x02
+#define HCM_BUS_RANGE             0x02
+#define TIP_BUS_OFFSET            0x01
+#define VID_BUS_OFFSET            0x01
+#define TIP_MMIO_SIZE             0x80000            // 512K MMIO resource for TIP
+#define VID_MMIO_SIZE             0x1000000          // 16MB MMIO resource for VID
+#define TIP_RESERVED_BUS          0x01
+#define VID_RESERVED_BUS          0x01
+
+#pragma pack(1)
+// It's better to align with UPD_IIO_PCIE_PORT_CONFIG
+typedef struct {
+  UINT8    SLOTEIP;
+  UINT8    SLOTHPCAP;
+  UINT8    SLOTHPSUP;
+  UINT8    SLOTPIP;
+  UINT8    SLOTAIP;
+  UINT8    SLOTMRLSP;
+  UINT8    SLOTPCP;
+  UINT8    SLOTABP;
+  UINT8    SLOTIMP;
+  UINT8    SLOTSPLS;
+  UINT8    SLOTSPLV;
+  UINT16   SLOTPSP;
+  BOOLEAN  VppEnabled;
+  UINT8    VppPort;
+  UINT8    VppAddress;
+  UINT8    MuxAddress;
+  UINT8    ChannelID;
+  UINT8    PciePortEnable;
+  UINT8    PEXPHIDE;
+  UINT8    HidePEXPMenu;
+  UINT8    PciePortOwnership;
+  UINT8    RetimerConnectCount;
+  UINT8    ConfigIOU;
+  UINT8    PcieHotPlugOnPort;
+  UINT8    VMDEnabled;
+  UINT8    VMDPortEnable;
+  UINT8    VMDHotPlugEnable;
+  UINT8    PcieMaxPayload;
+  UINT8    PciePortLinkSpeed;
+  UINT8    DfxDnTxPresetGen3;
+} UPD_IIO_PCIE_PORT_CONFIG_ENTRY;
+#pragma pack()
+
+//------------------------------------------------------------------------------------
+// Uncomment line(s) below to override macro definitions in FSP IioUniversalDataHob.h
+//------------------------------------------------------------------------------------
+// #define MAX_SOCKET                4
+// #define MAX_IMC                   4
+// #define MAX_CH                    8
+// #define MAX_IIO_PORTS_PER_SOCKET  57
+// #define MAX_IIO_STACK             12
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h
new file mode 100644
index 0000000..9f04b93
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h
@@ -0,0 +1,71 @@
+/** @file
+
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+**/
+
+#ifndef __DEFS_MEMMAP_H__
+#define __DEFS_MEMMAP_H__
+
+/* Bit definitions for RasModes */
+#define CH_INDEPENDENT		0
+#define FULL_MIRROR_1LM		BIT0
+#define FULL_MIRROR_2LM		BIT1
+#define CH_LOCKSTEP		BIT2
+#define RK_SPARE		BIT3
+#define PARTIAL_MIRROR_1LM	BIT5
+#define PARTIAL_MIRROR_2LM	BIT6
+#define STAT_VIRT_LOCKSTEP	BIT7
+
+#define MEMTYPE_1LM_MASK       (1 << 0)
+#define MEMTYPE_2LM_MASK       (1 << 1)
+#define MEMTYPE_VOLATILE_MASK  (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK)
+
+/* ACPI SRAT Memory Flags */
+#define SRAT_ACPI_MEMORY_ENABLED               (1 << 0)
+#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED  (1 << 1)
+#define SRAT_ACPI_MEMORY_NONVOLATILE           (1 << 2)
+
+#define MEM_TYPE_RESERVED (1 << 8)
+#define MEM_ADDR_64MB_SHIFT_BITS 26
+
+//------------------------------------------------------------------------------------
+// Uncomment line(s) below to override macro definitions in FSP MemoryMapDataHob.h
+//------------------------------------------------------------------------------------
+// #define MAX_UNIQUE_NGN_DIMM_INTERLEAVE    2
+// #define MAX_SPARE_RANK                    2
+// #define MAX_SOCKET                4     // Potentially need to refactor
+// #define MAX_IMC                   4   // Potentially need to refactor
+// #define MAX_HBM_IO                        4
+// #define MAX_MC_CH                         2
+// #define MAX_DIMM                          2                         // Max DIMM per channel
+// #define MAX_RANK_DIMM                     2
+// #define MAX_DRAM_CLUSTERS                 4
+// #define MAX_SAD_RULES                     16
+// #define MAX_FPGA_REMOTE_SAD_RULES         2     // Maximum FPGA sockets exists on ICX platform
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_cxlnode.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_cxlnode.h
new file mode 100644
index 0000000..2221a38
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_cxlnode.h
@@ -0,0 +1,40 @@
+/** @file
+  CXL GUID HOB definitions
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 1999 - 2021 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _HOB_CXLNODE_H_
+#define _HOB_CXLNODE_H_
+
+#include <fsp/util.h>
+#include "CxlNodeHob.h"
+
+#define FSP_HOB_CXLNODE_GUID { \
+	0x09, 0xe0, 0x8a, 0xdd, 0x5a, 0xda, 0xa3, 0x44, \
+	0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c  \
+}
+
+#endif //_HOB_CXLNODE_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_enhancedwarningloglib.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_enhancedwarningloglib.h
new file mode 100644
index 0000000..1a86caa
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_enhancedwarningloglib.h
@@ -0,0 +1,40 @@
+/** @file
+  Interface header file for the Enhanced warning log library class.
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 2018 - 2021 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _HOB_ENHANCEDWARNINGLOG_H_
+#define _HOB_ENHANCEDWARNINGLOG_H_
+
+#include <fsp/util.h>
+#include "EnhancedWarningLogLib.h"
+
+#define FSP_HOB_EWLID_GUID { \
+  0x00, 0x58, 0xe0, 0xd8, 0x5e, 0x00, 0x62, 0x44,\
+  0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0x0b \
+}
+
+#endif //_HOB_ENHANCEDWARNINGLOG_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_iiouds.h
new file mode 100644
index 0000000..1a61c1d
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_iiouds.h
@@ -0,0 +1,186 @@
+/**
+Copyright (c) 2019-2021, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+**/
+
+
+#ifndef _HOB_IIOUDS_H_
+#define _HOB_IIOUDS_H_
+
+#include <fsp/util.h>
+
+#include "defs_iio.h"
+#include "IioUniversalDataHob.h"
+
+#define FSP_HOB_IIO_UNIVERSAL_DATA_GUID { \
+	0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \
+	0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0  \
+}
+
+#define NUMBER_PORTS_PER_SOCKET  MAX_IIO_PORTS_PER_SOCKET
+
+#pragma pack(1)
+
+/**
+ * IIO Stacks
+ *
+ * Ports(XCC)  Stack(HOB)  IioConfigIou
+ * =========================================
+ * 0           stack 0     DmiAsPcie
+ * 1A..1H      stack 1     IOU0
+ * 2A..2H      stack 2     IOU1
+ * 3A..3H      stack 3     IOU2
+ * 4A..4H      stack 4     IOU3
+ * 5A..5H      stack 5     IOU4
+ * 6A..6H      stack 6     IOU5
+ */
+
+/**
+ IIO PCIe Ports
+ **/
+
+typedef enum {
+	// DmiAsPcie, stack 0
+	PORT_0 = 0,
+	// IOU0, stack 1
+	PORT_1A,
+	PORT_1B,
+	PORT_1C,
+	PORT_1D,
+	PORT_1E,
+	PORT_1F,
+	PORT_1G,
+	PORT_1H,
+	// IOU1, stack 2
+	PORT_2A,
+	PORT_2B,
+	PORT_2C,
+	PORT_2D,
+	PORT_2E,
+	PORT_2F,
+	PORT_2G,
+	PORT_2H,
+	// IOU2, stack 3
+	PORT_3A,
+	PORT_3B,
+	PORT_3C,
+	PORT_3D,
+	PORT_3E,
+	PORT_3F,
+	PORT_3G,
+	PORT_3H,
+	// IOU3, stack 4
+	PORT_4A,
+	PORT_4B,
+	PORT_4C,
+	PORT_4D,
+	PORT_4E,
+	PORT_4F,
+	PORT_4G,
+	PORT_4H,
+	// IOU4, stack 5
+	PORT_5A,
+	PORT_5B,
+	PORT_5C,
+	PORT_5D,
+	PORT_5E,
+	PORT_5F,
+	PORT_5G,
+	PORT_5H,
+	// IOU5, stack 6, not used for socket 0; for socket 1, swap from DMI as x8
+	PORT_6A,
+	PORT_6B,
+	PORT_6C,
+	PORT_6D,
+	PORT_6E,
+	PORT_6F,
+	PORT_6G,
+	PORT_6H,
+	// IOU6, stack 7, not used
+	PORT_7A,
+	PORT_7B,
+	PORT_7C,
+	PORT_7D,
+	PORT_7E,
+	PORT_7F,
+	PORT_7G,
+	PORT_7H,
+
+	MAX_PORTS
+} PCIE_PORTS;
+
+typedef enum {
+  //for ICX
+  IioStack0 = 0,	// DmiAsPcie
+  IioStack1 = 1,	// IOU0
+  IioStack2 = 2,	// IOU1
+  IioStack3 = 3,	// IOU2
+  IioStack4 = 4,	// IOU3
+  IioStack5 = 5,	// IOU4
+  //for SPR
+  IioStack6 = 6,	// IOU5
+  IioStack7 = 7,
+  IioStack8 = 8,
+  IioStack9 = 9,
+  IioStack10 = 10,
+  IioStack11 = 11,
+  //for later SOC
+  IioStack12 = 12,
+  IioStack13 = 13,
+  IioStack14 = 14,
+  IioStack15 = 15,
+  IioStack16 = 16,
+  IioStack17 = 17,
+  IioStack18 = 18,
+  IioStackUnknown = 0xFF
+} IIO_STACK;
+
+typedef enum {
+	TYPE_UBOX = 0,
+	TYPE_UBOX_IIO,
+	TYPE_MCP,
+	TYPE_FPGA,
+	TYPE_HFI,
+	TYPE_NAC,
+	TYPE_GRAPHICS,
+	TYPE_DINO,
+	TYPE_RESERVED,
+	TYPE_DISABLED,              // This item must be prior to stack specific disable types
+	TYPE_UBOX_IIO_DIS,
+	TYPE_MCP_DIS,
+	TYPE_FPGA_DIS,
+	TYPE_HFI_DIS,
+	TYPE_NAC_DIS,
+	TYPE_GRAPHICS_DIS,
+	TYPE_DINO_DIS,
+	TYPE_RESERVED_DIS,
+	TYPE_NONE
+} STACK_TYPE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h
new file mode 100644
index 0000000..8eb8960
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h
@@ -0,0 +1,48 @@
+/** @file
+  GUID used for Memory Map Data entries in the HOB list.
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 1999 - 2021 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _HOB_MEMMAP_H_
+#define _HOB_MEMMAP_H_
+
+#include "defs_memmap.h"
+#include "MemoryMapDataHob.h"
+
+#define FSP_SYSTEM_MEMORYMAP_HOB_GUID { \
+	0x15, 0x00, 0x87, 0xf8, 0x94, 0x69, 0x98, 0x4b, 0x95, 0xa2, \
+	0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \
+	}
+
+#define MAX_IMC_PER_SOCKET                MAX_IMC
+#define MAX_SRAT_MEM_ENTRIES_PER_IMC      8
+#define MAX_SMB_INSTANCE                  2
+#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \
+	MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \
+	)
+#define AMT_MAX_NODE        ((MAX_AMT)*(MAX_SOCKET))   // Max abstract memory target for all sockets
+
+#endif // _HOB_MEMMAP_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_systeminfo.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_systeminfo.h
new file mode 100644
index 0000000..0901651
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_systeminfo.h
@@ -0,0 +1,54 @@
+/** @file
+  System Information HOB Hearder File
+
+  @copyright
+  INTEL CONFIDENTIAL
+  Copyright 2017 - 2021 Intel Corporation. <BR>
+
+  The source code contained or described herein and all documents related to the
+  source code ("Material") are owned by Intel Corporation or its suppliers or
+  licensors. Title to the Material remains with Intel Corporation or its suppliers
+  and licensors. The Material may contain trade secrets and proprietary    and
+  confidential information of Intel Corporation and its suppliers and licensors,
+  and is protected by worldwide copyright and trade secret laws and treaty
+  provisions. No part of the Material may be used, copied, reproduced, modified,
+  published, uploaded, posted, transmitted, distributed, or disclosed in any way
+  without Intel's prior express written permission.
+
+  No license under any patent, copyright, trade secret or other intellectual
+  property right is granted to or conferred upon you by disclosure or delivery
+  of the Materials, either expressly, by implication, inducement, estoppel or
+  otherwise. Any license under such intellectual property rights must be
+  express and approved by Intel in writing.
+
+  Unless otherwise agreed by Intel in writing, you may not remove or alter
+  this notice or any other notice embedded in Materials by Intel or
+  Intel's suppliers or licensors in any way.
+**/
+
+#ifndef _HOB_SYSTEMINFO_H_
+#define _HOB_SYSTEMINFO_H_
+
+#include <fsp/util.h>
+#include "SystemInfoHob.h"
+
+typedef enum {
+  TypeLcc = 0,
+  TypeMcc,
+  TypeHcc,
+  TypeXcc,
+  TypeUcc,
+  TypeLccFb,
+  TypeZcc,
+  TypeX1,
+  TypeGrr,
+  TypeGnrd,
+  TypeChopTypeMax = 0xff
+} TYPE_CHOPTYPE_ENUM;
+
+#define FSP_HOB_SYSTEMINFO_GUID { \
+	0xf2, 0xa0, 0x50, 0x76, 0x91, 0x0d, 0x0c, 0x4b, \
+	0x92, 0x3b, 0xbd, 0xcf, 0x22, 0xd1, 0x64, 0x35  \
+}
+
+#endif //_HOB_SYSTEMINFO_H_