mb/google/brya/var/agah: Update GPU GPIOs
Converge as many of the GPU's GPIOs to use PLTRST# as the reset signal
explicitly, as the hardware engineers requested this.
BUG=none
TEST=boot and reboot agah, dGPU still visible on PCIe bus
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I78e58eb17cadc95083571affbecb4e1ce0adf16a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66809
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/brya/variants/agah/gpio.c b/src/mainboard/google/brya/variants/agah/gpio.c
index 007b7e4..2301da6 100644
--- a/src/mainboard/google/brya/variants/agah/gpio.c
+++ b/src/mainboard/google/brya/variants/agah/gpio.c
@@ -18,18 +18,18 @@
/* A15 : USB_OC2# ==> USB_C2_OC_ODL */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* A17 : DISP_MISCC ==> EN_GPU_PPVAR_GPU_NVVDD_X_PCH */
- PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+ PAD_CFG_GPI(GPP_A17, NONE, PLTRST),
/* A19 : DDSP_HPD1 ==> EN_PCH_PPVAR_GPU_FBVDDQ_X_L */
- PAD_CFG_GPO(GPP_A19, 1, DEEP),
+ PAD_CFG_GPO(GPP_A19, 1, PLTRST),
/* A20 : DDSP_HPD2 ==> NC */
PAD_NC(GPP_A20, NONE),
/* A21 : DDPC_CTRCLK ==> EN_PP3300_GPU_X */
- PAD_CFG_GPO(GPP_A21, 0, DEEP),
+ PAD_CFG_GPO(GPP_A21, 0, PLTRST),
/* A22 : DDPC_CTRCLK ==> PG_PP3300_GPU_X_OD */
PAD_CFG_GPI(GPP_A22, NONE, DEEP),
/* B3 : PROC_GP2 ==> GPU_PERST_L */
- PAD_CFG_GPO(GPP_B3, 0, DEEP),
+ PAD_CFG_GPO(GPP_B3, 0, PLTRST),
/* B5 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SDA */
PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
/* B6 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */
@@ -63,9 +63,9 @@
/* D3 : ISH_GP3 ==> NC */
PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D5 : SRCCLKREQ0# ==> GPU_CLKREQ_ODL */
- PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1),
/* D9 : ISH_SPI_CS# ==> GPU_THERM_INT_ODL */
- PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+ PAD_CFG_GPI(GPP_D9, NONE, PLTRST),
/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
/* D13 : ISH_UART0_RXD ==> NC */
@@ -82,7 +82,7 @@
/* E4 : SATA_DEVSLP0 ==> PG_PPVAR_GPU_FBVDDQ_X_OD */
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
/* E5 : SATA_DEVSLP1 ==> PG_GPU_ALLRAILS */
- PAD_CFG_GPO(GPP_E5, 0, DEEP),
+ PAD_CFG_GPO(GPP_E5, 0, PLTRST),
/* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE),
/* E9 : USB_OC0# ==> USB_A2_OC_ODL */
@@ -170,11 +170,13 @@
/* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
/* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
- PAD_CFG_GPO(GPP_D11, 1, DEEP),
+ PAD_CFG_GPO(GPP_D11, 1, PLTRST),
/* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+ /* E18 : DDP1_CTRLCLK ==> EN_PP1800_GPU_X */
+ PAD_CFG_GPO(GPP_E18, 0, PLTRST),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */