Revert "soc/intel/broadwell/pch: Drop device NVS remainders"
This reverts commit 34bd6ba97917b0bc54bb1f1e106a56b5c03e19ac.
Reason for revert: Device NVS is expected by mainboard samus
in payload depthcharge:
https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60
Not reverted:
* ACPI_HAS_DEVICE_NVS does not exist anymore in ToT and hence it's
selection in broadwell is not required.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic31d7ae62c5df72708b724160e96e10b46002eb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c
index 8c435d6..85726b0 100644
--- a/src/soc/intel/broadwell/pch/acpi.c
+++ b/src/soc/intel/broadwell/pch/acpi.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
-#include <assert.h>
+#include <soc/device_nvs.h>
#include <soc/pch.h>
#include <types.h>
#include <version.h>
@@ -54,32 +55,25 @@
acpigen_pop_len();
}
-static struct pch_acpi_device_state device_state[NUM_PCH_ACPI_DEVICES] = { 0 };
-
-struct pch_acpi_device_state *get_acpi_device_state(enum pch_acpi_device dev_index)
+static void acpi_create_serialio_ssdt_entry(int sio_index, struct device_nvs *dev_nvs)
{
- assert(dev_index < ARRAY_SIZE(device_state));
- return &device_state[dev_index];
-}
-
-static void acpi_create_serialio_ssdt_entry(enum pch_acpi_device dev_index)
-{
- const struct pch_acpi_device_state *state = get_acpi_device_state(dev_index);
-
- const char idx = '0' + dev_index;
+ const char idx = '0' + sio_index;
const char sxen[5] = { 'S', idx, 'E', 'N', '\0' };
- acpigen_write_name_byte(sxen, state->enable);
+ acpigen_write_name_byte(sxen, dev_nvs->enable[sio_index]);
const char sxb0[5] = { 'S', idx, 'B', '0', '\0' };
- acpigen_write_name_dword(sxb0, state->bar0);
+ acpigen_write_name_dword(sxb0, dev_nvs->bar0[sio_index]);
const char sxb1[5] = { 'S', idx, 'B', '1', '\0' };
- acpigen_write_name_dword(sxb1, state->bar1);
+ acpigen_write_name_dword(sxb1, dev_nvs->bar1[sio_index]);
}
void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
{
unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
+ if (!dev_nvs)
+ return;
/* Fill the SSDT header */
memset((void *)ssdt, 0, sizeof(acpi_header_t));
@@ -94,17 +88,17 @@
acpigen_set_current((char *)current);
/* Fill the SSDT with an entry for each SerialIO device */
- for (enum pch_acpi_device dev_index = 0; dev_index < NUM_PCH_ACPI_DEVICES; dev_index++)
- acpi_create_serialio_ssdt_entry(dev_index);
+ for (int id = 0; id < 9; id++)
+ acpi_create_serialio_ssdt_entry(id, dev_nvs);
acpigen_write_scope("\\_SB.PCI0");
{
- acpi_write_serialio_psx_methods("I2C0", device_state[PCH_ACPI_I2C0].bar1);
- acpi_write_serialio_psx_methods("I2C1", device_state[PCH_ACPI_I2C1].bar1);
- acpi_write_serialio_psx_methods("SPI0", device_state[PCH_ACPI_GSPI0].bar1);
- acpi_write_serialio_psx_methods("SPI1", device_state[PCH_ACPI_GSPI1].bar1);
- acpi_write_serialio_psx_methods("UAR0", device_state[PCH_ACPI_UART0].bar1);
- acpi_write_serialio_psx_methods("UAR1", device_state[PCH_ACPI_UART1].bar1);
+ acpi_write_serialio_psx_methods("I2C0", dev_nvs->bar1[SIO_NVS_I2C0]);
+ acpi_write_serialio_psx_methods("I2C1", dev_nvs->bar1[SIO_NVS_I2C1]);
+ acpi_write_serialio_psx_methods("SPI0", dev_nvs->bar1[SIO_NVS_SPI0]);
+ acpi_write_serialio_psx_methods("SPI1", dev_nvs->bar1[SIO_NVS_SPI1]);
+ acpi_write_serialio_psx_methods("UAR0", dev_nvs->bar1[SIO_NVS_UART0]);
+ acpi_write_serialio_psx_methods("UAR1", dev_nvs->bar1[SIO_NVS_UART1]);
}
acpigen_pop_len();
diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/soc/intel/broadwell/pch/adsp.c
index 3cc7e12..1ebf922 100644
--- a/src/soc/intel/broadwell/pch/adsp.c
+++ b/src/soc/intel/broadwell/pch/adsp.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -7,6 +8,8 @@
#include <device/pci_ops.h>
#include <device/mmio.h>
#include <soc/adsp.h>
+#include <soc/device_nvs.h>
+#include <soc/device_nvs.h>
#include <soc/pch.h>
#include <soc/rcba.h>
#include <soc/intel/broadwell/pch/chip.h>
@@ -75,14 +78,15 @@
pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
if (config->sio_acpi_mode) {
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
+
/* Configure for ACPI mode */
printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n");
- /* Save BAR0 and BAR1 */
- struct pch_acpi_device_state *state = get_acpi_device_state(PCH_ACPI_ADSP);
- state->enable = 1;
- state->bar0 = (u32)bar0->base;
- state->bar1 = (u32)bar1->base;
+ /* Save BAR0 and BAR1 to ACPI NVS */
+ dev_nvs->bar0[SIO_NVS_ADSP] = (u32)bar0->base;
+ dev_nvs->bar1[SIO_NVS_ADSP] = (u32)bar1->base;
+ dev_nvs->enable[SIO_NVS_ADSP] = 1;
/* Set PCI Config Disable Bit */
pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD);
diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/soc/intel/broadwell/pch/serialio.c
index 601bf97..e38de5e 100644
--- a/src/soc/intel/broadwell/pch/serialio.c
+++ b/src/soc/intel/broadwell/pch/serialio.c
@@ -2,10 +2,12 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
+#include <acpi/acpi_gnvs.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <soc/device_nvs.h>
#include <soc/pci_devs.h>
#include <soc/pch.h>
#include <soc/rcba.h>
@@ -156,7 +158,7 @@
{
const struct soc_intel_broadwell_pch_config *config = config_of(dev);
struct resource *bar0, *bar1;
- enum pch_acpi_device dev_index = NUM_PCH_ACPI_DEVICES;
+ int sio_index = -1;
printk(BIOS_DEBUG, "Initializing Serial IO device\n");
@@ -175,48 +177,54 @@
serialio_enable_clock(bar0);
switch (dev->path.pci.devfn) {
- case PCH_DEVFN_SDMA:
- dev_index = PCH_ACPI_SDMA;
+ case PCH_DEVFN_SDMA: /* SDMA */
+ sio_index = SIO_ID_SDMA;
serialio_init_once(config->sio_acpi_mode);
- serialio_d21_mode(SIO_ID_SDMA, SIO_PIN_INTB,
+ serialio_d21_mode(sio_index, SIO_PIN_INTB,
config->sio_acpi_mode);
break;
- case PCH_DEVFN_I2C0:
- dev_index = PCH_ACPI_I2C0;
+ case PCH_DEVFN_I2C0: /* I2C0 */
+ sio_index = SIO_ID_I2C0;
serialio_d21_ltr(bar0);
serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage);
- serialio_d21_mode(SIO_ID_I2C0, SIO_PIN_INTC, config->sio_acpi_mode);
+ serialio_d21_mode(sio_index, SIO_PIN_INTC,
+ config->sio_acpi_mode);
break;
- case PCH_DEVFN_I2C1:
- dev_index = PCH_ACPI_I2C1;
+ case PCH_DEVFN_I2C1: /* I2C1 */
+ sio_index = SIO_ID_I2C1;
serialio_d21_ltr(bar0);
serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage);
- serialio_d21_mode(SIO_ID_I2C1, SIO_PIN_INTC, config->sio_acpi_mode);
+ serialio_d21_mode(sio_index, SIO_PIN_INTC,
+ config->sio_acpi_mode);
break;
- case PCH_DEVFN_SPI0:
- dev_index = PCH_ACPI_GSPI0;
+ case PCH_DEVFN_SPI0: /* SPI0 */
+ sio_index = SIO_ID_SPI0;
serialio_d21_ltr(bar0);
- serialio_d21_mode(SIO_ID_SPI0, SIO_PIN_INTC, config->sio_acpi_mode);
+ serialio_d21_mode(sio_index, SIO_PIN_INTC,
+ config->sio_acpi_mode);
break;
- case PCH_DEVFN_SPI1:
- dev_index = PCH_ACPI_GSPI1;
+ case PCH_DEVFN_SPI1: /* SPI1 */
+ sio_index = SIO_ID_SPI1;
serialio_d21_ltr(bar0);
- serialio_d21_mode(SIO_ID_SPI1, SIO_PIN_INTC, config->sio_acpi_mode);
+ serialio_d21_mode(sio_index, SIO_PIN_INTC,
+ config->sio_acpi_mode);
break;
- case PCH_DEVFN_UART0:
- dev_index = PCH_ACPI_UART0;
+ case PCH_DEVFN_UART0: /* UART0 */
+ sio_index = SIO_ID_UART0;
if (!serialio_uart_is_debug(dev))
serialio_d21_ltr(bar0);
- serialio_d21_mode(SIO_ID_UART0, SIO_PIN_INTD, config->sio_acpi_mode);
+ serialio_d21_mode(sio_index, SIO_PIN_INTD,
+ config->sio_acpi_mode);
break;
- case PCH_DEVFN_UART1:
- dev_index = PCH_ACPI_UART1;
+ case PCH_DEVFN_UART1: /* UART1 */
+ sio_index = SIO_ID_UART1;
if (!serialio_uart_is_debug(dev))
serialio_d21_ltr(bar0);
- serialio_d21_mode(SIO_ID_UART1, SIO_PIN_INTD, config->sio_acpi_mode);
+ serialio_d21_mode(sio_index, SIO_PIN_INTD,
+ config->sio_acpi_mode);
break;
- case PCH_DEVFN_SDIO:
- dev_index = PCH_ACPI_SDIO;
+ case PCH_DEVFN_SDIO: /* SDIO */
+ sio_index = SIO_ID_SDIO;
serialio_d23_ltr(bar0);
serialio_d23_mode(config->sio_acpi_mode);
break;
@@ -225,14 +233,15 @@
}
if (config->sio_acpi_mode) {
- /* Save BAR0 and BAR1 */
- struct pch_acpi_device_state *state = get_acpi_device_state(dev_index);
- state->bar0 = (u32)bar0->base;
- state->bar1 = (u32)bar1->base;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
+
+ /* Save BAR0 and BAR1 to ACPI NVS */
+ dev_nvs->bar0[sio_index] = (u32)bar0->base;
+ dev_nvs->bar1[sio_index] = (u32)bar1->base;
if (!serialio_uart_is_debug(dev)) {
/* Do not enable UART if it is used as debug port */
- state->enable = 1;
+ dev_nvs->enable[sio_index] = 1;
/* Put device in D3hot state via BAR1 */
if (dev->path.pci.devfn != PCH_DEVFN_SDMA)