| commit | 92d49da1630e94cccdfbf4ec72371f66380d5fd7 | [log] [tgz] |
|---|---|---|
| author | zhaojohn <john.zhao@intel.com> | Fri Dec 16 09:27:19 2022 -0800 |
| committer | Martin L Roth <gaumless@gmail.com> | Sat Dec 24 23:37:56 2022 +0000 |
| tree | 24f78a68b5b13b45c330878c4896f40dcd77e1b3 | |
| parent | 387ec919d9f74947b84ed08d5eece8b2f0ca9cae [diff] |
mb/google/rex: Enable DPTF functionality for Rex Enable DPTF functionality for Meteor Lake Rex board. BUG=b:262498724 TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board. Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 7976e0b..54811ac 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig
@@ -4,6 +4,8 @@ select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF + select DRIVERS_INTEL_DPTF_SUPPORTS_TPCH select DRIVERS_INTEL_USB4_RETIMER select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_WIFI_GENERIC
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index cbfa49a..a3225ca 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -14,6 +14,9 @@ # S0ix enable register "s0ix_enable" = "1" + # DPTF enable + register "dptf_enable" = "1" + # Enable CNVi BT register "cnvi_bt_core" = "true"
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index b02999f..e7244cb 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -118,6 +118,11 @@ }" device domain 0 on + device ref dtt on + chip drivers/intel/dptf + device generic 0 alias dptf_policy on end + end + end device ref pcie_rp9 on # Enable SSD Card PCIE 9 using clk 4 register "pcie_rp[PCH_RP(9)]" = "{