sb/intel/ibexpeak/early_pch.c: Use PCI_BASE_ADDRESS_0 macro
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If74e1db623d65d639041d49caf0ca1b6c0e1f2ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c
index 9edbcf6..4df47f3 100644
--- a/src/southbridge/intel/ibexpeak/early_pch.c
+++ b/src/southbridge/intel/ibexpeak/early_pch.c
@@ -48,7 +48,8 @@
outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06);
printk(BIOS_DEBUG, " done.\n");
- pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR);
+ pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_BASE_ADDRESS_0,
+ (uintptr_t)DEFAULT_HECIBAR);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}