soc/intel/skylake: Enable HECI3 depending on devicetree configuration
Currently HECI3 gets enabled by the option Heci3Enabled, but
this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the HECI3 controller.
I checked all corresponding mainboards if the devicetree configuration
matches the Heci3Enabled setting.
Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 7dee333..a73aa8d 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -231,7 +231,9 @@
params->PchCio2Enable = config->Cio2Enable;
params->SaImguEnable = config->SaImguEnable;
- params->Heci3Enabled = config->Heci3Enabled;
+
+ dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
+ params->Heci3Enabled = dev ? dev->enabled : 0;
params->LogoPtr = config->LogoPtr;
params->LogoSize = config->LogoSize;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 54d0069..3f55c18 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -315,7 +315,6 @@
u8 PttSwitch;
u8 HeciTimeouts;
u8 HsioMessaging;
- u8 Heci3Enabled;
/* Gfx related */
u8 IgdDvmt50PreAlloc;