tree a3c64ce6710af1d96584a129dca5fa20a0fac285
parent 1858903e780391cac0f37157f5de821b508d4e8d
author Subrata Banik <subratabanik@google.com> 1695238121 +0000
committer Subrata Banik <subratabanik@google.com> 1696445432 +0000

soc/intel: Select GMA v2 for ADL, MTL, TGL to reflect port/pipe defs

Intel GFX IP TRANS_DDI_FUNC_CTL register bit definitions have changed
since Tiger Lake.

This register is used to map ports and pipes to display controllers,
so reflecting the correct status is important for detecting physical
display end point devices.

This patch ensures that ADL, MTL, and TGL SoCs choose GMA version 2 to
properly reflect the updated port and pipe register definitions.

BUG=b:299137940
TEST=Build and boot google/rex successfully.

Change-Id: Ie2082747d18a5f136f410b1019be4d6c801617b1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>