diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c
index 5080d9b..c444b4c 100644
--- a/src/mainboard/google/volteer/fw_config.c
+++ b/src/mainboard/google/volteer/fw_config.c
@@ -66,7 +66,7 @@
 	PAD_NC(GPP_R7, NONE),
 };
 
-static const struct pad_config sd_gl9755s_pads[] = {
+static const struct pad_config sd_power_enable_pads[] = {
 	PAD_CFG_GPO(GPP_D16, 1, DEEP),
 };
 
@@ -99,9 +99,12 @@
 		gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
 		gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
 	}
-	if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S))) {
-		printk(BIOS_INFO, "Configure GPIOs for SD GL9755S.\n");
-		gpio_configure_pads(sd_gl9755s_pads, ARRAY_SIZE(sd_gl9755s_pads));
+	if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S)) ||
+	    fw_config_probe(FW_CONFIG(DB_SD, SD_RTS5227S)) ||
+	    fw_config_probe(FW_CONFIG(DB_SD, SD_GL9750)) ||
+	    fw_config_probe(FW_CONFIG(DB_SD, SD_OZ711LV2LN))) {
+		printk(BIOS_INFO, "Configure GPIOs for SD power enable.\n");
+		gpio_configure_pads(sd_power_enable_pads, ARRAY_SIZE(sd_power_enable_pads));
 	}
 }
 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index bc1febb..455b9ab 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -39,7 +39,7 @@
 		option SD_GL9755S 1
 		option SD_RTS5261 2
 		option SD_RTS5227S 3
-		option SD_L9750 4
+		option SD_GL9750 4
 		option SD_OZ711LV2LN 5
 	end
 	field KB_LAYOUT 20 21
@@ -459,12 +459,18 @@
 		device ref pcie_rp8 on
 			probe DB_SD SD_GL9755S
 			probe DB_SD SD_RTS5261
+			probe DB_SD SD_RTS5227S
+			probe DB_SD SD_GL9750
+			probe DB_SD SD_OZ711LV2LN
 			chip soc/intel/common/block/pcie/rtd3
 				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)"
 				register "srcclk_pin" = "3"
 				device generic 0 on
 					probe DB_SD SD_GL9755S
+					probe DB_SD SD_RTS5227S
+					probe DB_SD SD_GL9750
+					probe DB_SD SD_OZ711LV2LN
 				end
 			end
 			chip soc/intel/common/block/pcie/rtd3