Add support for A-Open DXPL Plus-U motherboard
This is an old (pre-2005) entry-level server mainboard. The code
is adapted from mainboard/intel/xe7501devkit.
Featured chips:
- Dual socket604
- E7505 northbridge
- 82801DB southbridge (with EHCI debug port)
- 82870p2 PCI-X bridge
- LPC47M102S-MC super-io
- 512kB FWH flash (flashrom does the job well)
What works:
- Dual-Xeon P4/HT boot with microcode update
- RAM: registered ECC DDR266 in dual-channel
- PCI-X slot interrupts with ACPI and I/O apic
- On-board PCI-X GbE and SCSI
- ACPI power-off and wakeup with PME#
Notes :
- Current ACPI is more or less a mess
- Interrupts do not route correctly with PIRQ
- MP-table is not implemented
- Issues with reboots remain (cold and warm)
- Many superio devices are disabled by default
- Audio codec is not investigated
Change-Id: I02d18c83f485a09ada65dde03bcc86e9163f2011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/303
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl
new file mode 100644
index 0000000..3958699
--- /dev/null
+++ b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Interrupt routing for PCI 03:xx.x */
+
+/* I/O APIC id 0x3 */
+Device(PBIO)
+{
+ Name (_HID, "ACPI000A")
+ Name (_ADR, 0x001c0000)
+}
+
+/* PCI-X bridge */
+Device(P64B)
+{
+ Name (_ADR, 0x001d0000)
+ Name (_PRT, Package() {
+ Package() { 0x0002ffff, 0, 0, 24 }, /* PCI-X slot 1 */
+ Package() { 0x0002ffff, 1, 0, 25 },
+ Package() { 0x0002ffff, 2, 0, 26 },
+ Package() { 0x0002ffff, 3, 0, 27 },
+ Package() { 0x0003ffff, 0, 0, 28 }, /* PCI-X slot 2 */
+ Package() { 0x0003ffff, 1, 0, 29 },
+ Package() { 0x0003ffff, 2, 0, 30 },
+ Package() { 0x0003ffff, 3, 0, 31 },
+ Package() { 0x0004ffff, 0, 0, 32 }, /* On-board GbE */
+ })
+
+ Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
+ OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)
+ Field (PBPC, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x3E), BCRL, 8, BCRH, 8
+ }
+
+
+ Device (ETH0)
+ {
+ Name (_ADR, 0x00040000)
+ Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
+ }
+}
+
+
+/* Interrupt routing for PCI 04:xx.x */
+
+/* I/O APIC id 0x4 */
+Device(PAIO)
+{
+ Name (_HID, "ACPI000A")
+ Name (_ADR, 0x001e0000)
+}
+
+/* PCI-X bridge */
+Device(P64A)
+{
+ Name (_ADR, 0x001f0000)
+ Name (_PRT, Package() {
+ Package() { 0x0002ffff, 0, 0, 48 }, /* PCI-X slot 3 */
+ Package() { 0x0002ffff, 1, 0, 49 },
+ Package() { 0x0002ffff, 2, 0, 50 },
+ Package() { 0x0002ffff, 3, 0, 51 },
+ Package() { 0x0003ffff, 0, 0, 52 }, /* PCI-X slot 4 */
+ Package() { 0x0003ffff, 1, 0, 53 },
+ Package() { 0x0003ffff, 2, 0, 54 },
+ Package() { 0x0003ffff, 3, 0, 55 },
+ Package() { 0x0004ffff, 0, 0, 54 }, /* On-board SCSI, GSI not 56 ? */
+ Package() { 0x0004ffff, 1, 0, 55 }, /* On-board SCSI, GSI not 57 */
+ })
+
+ Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
+ OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)
+ Field (PBPC, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x3E), BCRL, 8, BCRH, 8
+ }
+
+ #include "acpi/scsi.asl"
+}
+
+