Add support for Supermicro H8scm.
It is AMD C32 + SR5650 + SP5100.
It is created by svn copy amd/tilapia_fam10.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
new file mode 100644
index 0000000..c6ccecb
--- /dev/null
+++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
@@ -0,0 +1,139 @@
+# GPP1 (dev2,3) --> slot 7
+# GPP2 (dev12) --> slot 6
+# GPP3A (dev9,A) --> Lan1, Lan2
+
+# sample config for supermicro/h8scm_fam10
+chip northbridge/amd/amdfam10/root_complex
+ device lapic_cluster 0 on
+ chip cpu/amd/socket_C32 #L1 and DDR3
+ device lapic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ subsystemid 0x15d9 0x1511 inherit
+ chip northbridge/amd/amdfam10
+ ##device pci 18.0 on end
+ ##device pci 18.0 on end
+ device pci 18.0 on # northbridge
+ chip southbridge/amd/sr5650
+ device pci 0.0 on end # HT 0x9600
+ device pci 0.1 on end # CLKCONFIG
+ device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
+ device pci 3.0 off end # PCIE P2P bridge 0x960b
+ device pci 4.0 off end # PCIE P2P bridge 0x9604
+ device pci 5.0 off end # PCIE P2P bridge 0x9605
+ device pci 6.0 on end # PCIE P2P bridge 0x9606
+ device pci 7.0 on end # PCIE P2P bridge 0x9607
+ device pci 8.0 on end # NB/SB Link P2P bridge
+ device pci 9.0 on end #
+ device pci a.0 on end #
+ device pci b.0 on end #
+ device pci c.0 on end #
+ device pci d.0 on end #
+ register "gpp1_configuration" = "0" # Configuration 16:0 default
+ register "gpp2_configuration" = "1" # Configuration 8:8
+ #register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0
+ register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1
+ register "port_enable" = "0x1ffc"
+ end
+ chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pri bus
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.1 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.1 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on end # SM
+ device pci 14.1 on end # IDE 0x439c
+ device pci 14.2 off end # HDA 0x4383, h8scm doesnt have codec.
+ device pci 14.3 on # LPC 0x439d
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 off # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # SFI
+ io 0x62 = 0x100
+ end
+ device pnp 2e.7 off # GPIO_GAME_MIDI
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # WDTO_PLED
+ device pnp 2e.9 off end # GPIO_SUSLED
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end #superio/winbond/w83627hf
+ end #LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # USB 2
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ end #southbridge/amd/sp5100
+ end # device pci 18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ device pci 19.4 on end
+ end
+ end #pci_domain
+ #for node 32 to node 63
+# device pci_domain 0 on
+# chip northbridge/amd/amdfam10
+# device pci 00.0 on end# northbridge
+# device pci 00.0 on end
+# device pci 00.0 on end
+# device pci 00.0 on end
+# device pci 00.1 on end
+# device pci 00.2 on end
+# device pci 00.3 on end
+# device pci 00.4 on end
+# device pci 00.5 on end
+# end
+# end #pci_domain
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 off end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# device pnp 0.8 off end # hard reset
+# device pnp 0.9 off end # mcp55
+# device pnp 0.a on end # GH ext table
+# end
+
+end
+
+