nb/intel/pineview: Refactor `decode_pcie_bar`
Constify and eliminate local variables where possible to ease reading.
Tested with BUILD_TIMELESS, Foxconn D41S remains identical.
Change-Id: Iaad759886a8f5ac07aabdea8ab1c6d1aa7020dfc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index ab0f31b..146fff2 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -19,11 +19,7 @@
{
*base = 0;
*len = 0;
- const pci_devfn_t dev = HOST_BRIDGE;
- u32 pciexbar = 0;
- u32 pciexbar_reg;
- u32 reg32;
- int max_buses;
+
const struct {
u16 num_buses;
u32 addr_mask;
@@ -34,7 +30,7 @@
{0, 0},
};
- pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+ const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, PCIEXBAR);
/* MMCFG not supported or not enabled */
if (!(pciexbar_reg & (1 << 0))) {
@@ -42,9 +38,9 @@
return 0;
}
- reg32 = (pciexbar_reg >> 1) & 3;
- pciexbar = pciexbar_reg & busmask[reg32].addr_mask;
- max_buses = busmask[reg32].num_buses;
+ const u32 index = (pciexbar_reg >> 1) & 3;
+ const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
+ const int max_buses = busmask[index].num_buses;
if (!pciexbar) {
printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");