tree fda9a9544b4dfebf426ac3cefad002f03b0ca3a3
parent c46cadd22bb4fc4bbb0a77a42afd83f9b323fb57
author Subrata Banik <subratabanik@google.com> 1641381216 +0000
committer Subrata Banik <subratabanik@google.com> 1641482342 +0000

soc/intel/alderlake: Fix GPIO reset mapping as per GPIO BWG

This patch fixes the documentation discrepancy of GPIO reset type
between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO
reset types in Alder Lake as below:
- Power Good - (Value 00)
- Deep - (Value 01)
- Host Reset/PLTRST - (Value 10)
- RSMRST for GPD/Reserved for GPP - (Value 11)

Hence, created two different reset types for `GPP` and `GPD`.
Also, replaced PAD_CFG0_LOGICAL_RESET_x macros with PAD_RESET().

BUG=b:213293047

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4b8742c7a0cc1dc420e3e22e34a16355294ed61b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>