mb/google/hades: update TPM IRQ in early gpio table
TPM IRQ should be A20 not A13. RAM table is correct.
BUG=b:282164589
TEST=able to boot up
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I82a709cc280288d612c65697b8da3c4274d4cd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75191
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/brya/variants/hades/gpio.c b/src/mainboard/google/brya/variants/hades/gpio.c
index e0588c3..d0a7cc2 100644
--- a/src/mainboard/google/brya/variants/hades/gpio.c
+++ b/src/mainboard/google/brya/variants/hades/gpio.c
@@ -383,7 +383,7 @@
/* GPP_A12 : [] ==> EN_PPVAR_WWAN */
PAD_CFG_GPO(GPP_A12, 1, DEEP),
/* GPP_A13 : [] ==> GSC_PCH_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+ PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT),
/* GPP_B4 : [] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* GPP_B7 : [] ==> PCH_I2C_TPM_SDA */