commit 9059a8987892503c31f77ac9aba4ca2bacf3e3af
author Arthur Heymans <arthur@aheymans.xyz> Fri Oct 23 11:08:41 2020 +0200
committer Hung-Te Lin <hungte@chromium.org> Tue Dec 29 14:41:15 2020 +0000
tree 683279c09282af709c022a1ca379a958864d80f9
parent 41b5b045ddca9286dab6b5345b6adba06514c1f1

sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurable

More recent platforms (Cooperlake) need bigger sizes.

Change-Id: Ia3e81d051a03b54233eef6ccdc4740c1a709be40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/security/intel/txt/ramstage.c

diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c
index 81d2dd1..c33af89 100644
--- a/src/security/intel/txt/ramstage.c
+++ b/src/security/intel/txt/ramstage.c
@@ -372,6 +372,9 @@
 			return;
 		}
 
+		_Static_assert(CONFIG_INTEL_TXT_HEAP_SIZE + CONFIG_INTEL_TXT_SINIT_SIZE
+			       < CONFIG_INTEL_TXT_DPR_SIZE * MiB, "TXT Heap and Sinit must fit DPR");
+
 		if (dpr.size < CONFIG_INTEL_TXT_DPR_SIZE) {
 			printk(BIOS_ERR, "TEE-TXT: MCH DPR configured size is too small.\n");
 			return;
@@ -396,7 +399,7 @@
 	 * Document Number: 558294
 	 * Chapter 5.5.6.3 Intel TXT Heap Memory Region
 	 */
-	write64((void *)TXT_HEAP_SIZE, 0xE0000);
+	write64((void *)TXT_HEAP_SIZE, CONFIG_INTEL_TXT_HEAP_SIZE);
 	write64((void *)TXT_HEAP_BASE,
 		ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096));
 
@@ -404,7 +407,7 @@
 	 * Document Number: 558294
 	 * Chapter 5.5.6.2 SINIT Memory Region
 	 */
-	write64((void *)TXT_SINIT_SIZE, 0x20000);
+	write64((void *)TXT_SINIT_SIZE, CONFIG_INTEL_TXT_SINIT_SIZE);
 	write64((void *)TXT_SINIT_BASE,
 		ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) -
 			   read64((void *)TXT_SINIT_SIZE), 4096));