src/soc/intel: Remove unnecessary space after casts
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c
index 712c128..83531de 100644
--- a/src/soc/intel/alderlake/bootblock/pch.c
+++ b/src/soc/intel/alderlake/bootblock/pch.c
@@ -54,7 +54,7 @@
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */
- setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
+ setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
}
void bootblock_pch_early_init(void)
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 26eba76..853b2f2 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -594,7 +594,7 @@
* This would avoid APs from getting hijacked by FSP while coreboot
* decides to set SkipMpInit UPD.
*/
- s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+ s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
if (CONFIG(USE_FSP_MP_INIT))
/*
diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c
index 9389322..e6aeed8 100644
--- a/src/soc/intel/alderlake/pmutil.c
+++ b/src/soc/intel/alderlake/pmutil.c
@@ -253,7 +253,7 @@
/* STM Support */
uint16_t get_pmbase(void)
{
- return (uint16_t) ACPI_BASE_ADDRESS;
+ return (uint16_t)ACPI_BASE_ADDRESS;
}
/*
diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c
index 9a8532d..36fa45b 100644
--- a/src/soc/intel/alderlake/systemagent.c
+++ b/src/soc/intel/alderlake/systemagent.c
@@ -84,9 +84,9 @@
{
msr_t msr;
msr = rdmsr(MSR_PRMRR_BASE_0);
- *prmrr_base = (uint64_t) msr.hi << 32 | msr.lo;
+ *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo;
msr = rdmsr(MSR_PRMRR_PHYS_MASK);
- *prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo;
+ *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo;
return 0;
}
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 811c762..a537b0f 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -77,7 +77,7 @@
/* Assign address of PERST_0 if GPIO is defined in devicetree */
if (cfg->prt0_gpio != GPIO_PRT0_UDEF)
- gnvs->prt0 = (uintptr_t) gpio_dwx_address(cfg->prt0_gpio);
+ gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio);
/* Get sdcard cd GPIO portid if GPIO is defined in devicetree.
* Get offset of sdcard cd pin.
@@ -216,7 +216,7 @@
static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
{
assert(gpio_num < TOTAL_PADS);
- uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num);
+ uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num);
acpigen_soc_get_dw0_in_local5(addr);
@@ -240,7 +240,7 @@
static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
{
assert(gpio_num < TOTAL_PADS);
- uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num);
+ uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num);
acpigen_soc_get_dw0_in_local5(addr);
diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c
index 01c4c47..46bc8fb 100644
--- a/src/soc/intel/apollolake/cse.c
+++ b/src/soc/intel/apollolake/cse.c
@@ -117,7 +117,7 @@
{
uint8_t buff;
- write8(&buff, (uint8_t) state);
+ write8(&buff, (uint8_t)state);
return rdev_writeat(rdev, &buff, 0, sizeof(buff));
}
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index f474553..878b2a6 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -221,7 +221,7 @@
/* STM Support */
uint16_t get_pmbase(void)
{
- return (uint16_t) ACPI_BASE_ADDRESS;
+ return (uint16_t)ACPI_BASE_ADDRESS;
}
void pmc_soc_set_afterg3_en(const bool on)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 757bad3..b9ec4e2 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -294,7 +294,7 @@
parse_devicetree_setting(mupd);
/* Do NOT let FSP do any GPIO pad configuration */
- mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL;
+ mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t)NULL;
mupd->FspmConfig.SkipCseRbp = CONFIG(SKIP_CSE_RBP);
diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c
index f352f8a..b61f5fa 100644
--- a/src/soc/intel/apollolake/systemagent.c
+++ b/src/soc/intel/apollolake/systemagent.c
@@ -70,7 +70,7 @@
printk(BIOS_ERR, "Incorrect PRMRR base hob size\n");
return -1;
}
- *prmrr_base = *(uint64_t *) hob;
+ *prmrr_base = *(uint64_t *)hob;
hob = fsp_find_extension_hob_by_guid(prmrr_size_guid,
&hob_size);
@@ -82,7 +82,7 @@
printk(BIOS_ERR, "Incorrect PRMRR base hob size\n");
return -1;
}
- prmrr_size = *(uint64_t *) hob;
+ prmrr_size = *(uint64_t *)hob;
phys_address_mask = (1ULL << cpu_phys_address_size()) - 1;
*prmrr_mask = phys_address_mask & ~(uint64_t)(prmrr_size - 1);
diff --git a/src/soc/intel/baytrail/refcode_native.c b/src/soc/intel/baytrail/refcode_native.c
index c915530..bc7a87c 100644
--- a/src/soc/intel/baytrail/refcode_native.c
+++ b/src/soc/intel/baytrail/refcode_native.c
@@ -29,21 +29,21 @@
static void gpio_sc_sdcard_workaround(void)
{
- setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0));
- setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 2));
- clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 1));
- clrbits32((char *) IO_BASE_ADDRESS + 0x690, (1 << 3));
+ setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 0));
+ setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 2));
+ clrbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 1));
+ clrbits32((char *)IO_BASE_ADDRESS + 0x690, (1 << 3));
udelay(100);
- clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0));
+ clrbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 0));
udelay(100);
- write32((char *) IO_BASE_ADDRESS + 0x830, 0x78480);
+ write32((char *)IO_BASE_ADDRESS + 0x830, 0x78480);
udelay(40);
- write32((char *) IO_BASE_ADDRESS + 0x830, 0x78080);
- setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0));
+ write32((char *)IO_BASE_ADDRESS + 0x830, 0x78080);
+ setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 0));
udelay(100);
- setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 1));
- clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 2));
- clrsetbits32((char *) IO_BASE_ADDRESS + 0x690, 7, (1 << 0));
+ setbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 1));
+ clrbits32((char *)IO_BASE_ADDRESS + 0x698, (1 << 2));
+ clrsetbits32((char *)IO_BASE_ADDRESS + 0x690, 7, (1 << 0));
}
#define BUNIT_BALIMIT0 0x0b
@@ -99,10 +99,10 @@
program_modphy_table(revb0_modphy_table);
}
- setbits32((char *) PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1, 8);
+ setbits32((char *)PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1, 8);
for (pollcnt = 0; pollcnt < 10; ++pollcnt) {
- tmp = read32((char *) PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1);
+ tmp = read32((char *)PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1);
printk(BIOS_DEBUG, "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", tmp);
if (!(tmp & 8))
break;
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 27f38ea..230c6dee 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -114,7 +114,7 @@
printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
return;
}
- printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base);
+ printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32)res->base);
/* Continue using old way of informing firmware address / size. */
pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base);
diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c
index 4650a224..f1750d2 100644
--- a/src/soc/intel/broadwell/pch/me.c
+++ b/src/soc/intel/broadwell/pch/me.c
@@ -598,7 +598,7 @@
u16 reg16;
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0)
return;
/* Make sure IO is disabled */
diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c
index 3da6bce..931dcc9 100644
--- a/src/soc/intel/broadwell/pch/pmutil.c
+++ b/src/soc/intel/broadwell/pch/pmutil.c
@@ -425,5 +425,5 @@
/* STM Support */
uint16_t get_pmbase(void)
{
- return (uint16_t) ACPI_BASE_ADDRESS;
+ return (uint16_t)ACPI_BASE_ADDRESS;
}
diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c
index 9f929a4..edb9830 100644
--- a/src/soc/intel/broadwell/pch/sata.c
+++ b/src/soc/intel/broadwell/pch/sata.c
@@ -82,8 +82,8 @@
/* PI (Ports implemented) */
write32(abar + 0x0c, config->sata_port_map);
- (void) read32(abar + 0x0c); /* Read back 1 */
- (void) read32(abar + 0x0c); /* Read back 2 */
+ (void)read32(abar + 0x0c); /* Read back 1 */
+ (void)read32(abar + 0x0c); /* Read back 2 */
/* CAP2 (HBA Capabilities Extended)*/
if (config->sata_devslp_disable) {
diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c
index 9d4bd2d..ee54f19 100644
--- a/src/soc/intel/broadwell/refcode.c
+++ b/src/soc/intel/broadwell/refcode.c
@@ -50,7 +50,7 @@
broadwell_fill_pei_data(&pei_data);
pei_data.boot_mode = acpi_is_wakeup_s3() ? ACPI_S3 : 0;
- pei_data.saved_data = (void *) &dummy;
+ pei_data.saved_data = (void *)&dummy;
entry = load_reference_code();
if (entry == NULL) {
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 7651cdf..8ec4782 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -56,7 +56,7 @@
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */
- setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
+ setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
}
void bootblock_pch_early_init(void)
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 7df8d47..480f65b 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -246,7 +246,7 @@
/* STM Support */
uint16_t get_pmbase(void)
{
- return (uint16_t) ACPI_BASE_ADDRESS;
+ return (uint16_t)ACPI_BASE_ADDRESS;
}
/*
diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c
index 239c72c..2bdf2cc 100644
--- a/src/soc/intel/common/block/crashlog/crashlog.c
+++ b/src/soc/intel/common/block/crashlog/crashlog.c
@@ -329,7 +329,7 @@
/* allocate mem for the record to be copied */
unsigned long pmc_cl_cbmem_addr;
- pmc_cl_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_PMC_CRASHLOG,
+ pmc_cl_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_PMC_CRASHLOG,
pmc_crashLog_size);
if (!pmc_cl_cbmem_addr) {
printk(BIOS_ERR, "Unable to allocate CBMEM PMC crashLog entry.\n");
@@ -337,7 +337,7 @@
}
memset((void *)pmc_cl_cbmem_addr, 0, pmc_crashLog_size);
- dest = (u32 *)(uintptr_t) pmc_cl_cbmem_addr;
+ dest = (u32 *)(uintptr_t)pmc_cl_cbmem_addr;
bool pmc_sram = true;
pmc_crashlog_desc_table_t descriptor_table = cl_get_pmc_descriptor_table();
if (discovery_buf.bits.discov_mechanism == 1) {
@@ -400,16 +400,16 @@
/* allocate memory buffers for CPU crashog data to be copied */
unsigned long cpu_crashlog_cbmem_addr;
- cpu_crashlog_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_CPU_CRASHLOG,
+ cpu_crashlog_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_CPU_CRASHLOG,
m_cpu_crashLog_size);
if (!cpu_crashlog_cbmem_addr) {
printk(BIOS_ERR, "Failed to add CPU main crashLog entries to CBMEM.\n");
return;
}
- memset((void *) cpu_crashlog_cbmem_addr, 0, m_cpu_crashLog_size);
+ memset((void *)cpu_crashlog_cbmem_addr, 0, m_cpu_crashLog_size);
tmp_bar_addr = cl_get_cpu_bar_addr();
- dest = (u32 *)(uintptr_t) cpu_crashlog_cbmem_addr;
+ dest = (u32 *)(uintptr_t)cpu_crashlog_cbmem_addr;
bool pmc_sram = false;
for (int i = 0 ; i < cpu_cl_disc_tab.header.fields.count ; i++) {
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index c2d4484..2cb3452 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -163,7 +163,7 @@
uint8_t wp, rp;
rp = data >> CSR_RP_START;
wp = data >> CSR_WP_START;
- return (uint8_t) (wp - rp);
+ return (uint8_t)(wp - rp);
}
static size_t cse_filled_slots(void)
@@ -571,7 +571,7 @@
} while (received && !(hdr & MEI_HDR_IS_COMPLETE) && left > 0);
if ((hdr & MEI_HDR_IS_COMPLETE) && received) {
- *maxlen = p - (uint8_t *) buff;
+ *maxlen = p - (uint8_t *)buff;
return CSE_TX_RX_SUCCESS;
}
}
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 37640f4..11a4624 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -526,7 +526,7 @@
return false;
printk(BIOS_DEBUG, "cse_lite: CSE RW partition: offset = 0x%x, size = 0x%x\n",
- (uint32_t)start_offset, (uint32_t) size);
+ (uint32_t)start_offset, (uint32_t)size);
return true;
}
@@ -930,8 +930,8 @@
struct subpart_entry *subpart_entry;
struct subpart_entry_manifest_header *man_hdr;
- subpart_entry = (struct subpart_entry *) (ptr + SUBPART_HEADER_SZ);
- man_hdr = (struct subpart_entry_manifest_header *) (ptr + subpart_entry->offset_bytes);
+ subpart_entry = (struct subpart_entry *)(ptr + SUBPART_HEADER_SZ);
+ man_hdr = (struct subpart_entry_manifest_header *)(ptr + subpart_entry->offset_bytes);
fw_ver->major = man_hdr->binary_version.major;
fw_ver->minor = man_hdr->binary_version.minor;
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index ea365d0..68bde41 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -580,9 +580,9 @@
dw1 = (gpio_cfg >> GPE0_DW_SHIFT(1)) & GPE0_DWX_MASK;
dw2 = (gpio_cfg >> GPE0_DW_SHIFT(2)) & GPE0_DWX_MASK;
} else {
- gpio_cfg |= (uint32_t) dw0 << GPE0_DW_SHIFT(0);
- gpio_cfg |= (uint32_t) dw1 << GPE0_DW_SHIFT(1);
- gpio_cfg |= (uint32_t) dw2 << GPE0_DW_SHIFT(2);
+ gpio_cfg |= (uint32_t)dw0 << GPE0_DW_SHIFT(0);
+ gpio_cfg |= (uint32_t)dw1 << GPE0_DW_SHIFT(1);
+ gpio_cfg |= (uint32_t)dw2 << GPE0_DW_SHIFT(2);
}
gpio_cfg_reg = read32p(pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
diff --git a/src/soc/intel/denverton_ns/pmutil.c b/src/soc/intel/denverton_ns/pmutil.c
index 8d670c6..2c9fc57 100644
--- a/src/soc/intel/denverton_ns/pmutil.c
+++ b/src/soc/intel/denverton_ns/pmutil.c
@@ -93,7 +93,7 @@
/* 4KiB alignment. */
reg32 &= ~0xfff;
- return (void *)(uintptr_t) reg32;
+ return (void *)(uintptr_t)reg32;
}
void disable_smi(uint32_t mask)
diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c
index 306908f..9541c4b 100644
--- a/src/soc/intel/elkhartlake/bootblock/pch.c
+++ b/src/soc/intel/elkhartlake/bootblock/pch.c
@@ -46,7 +46,7 @@
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */
- setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
+ setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
}
void bootblock_pch_early_init(void)
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index aacb1e6..c72d4da 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -269,7 +269,7 @@
/* Use coreboot MP PPI services if Kconfig is enabled */
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
- params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+ params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
/* Chipset Lockdown */
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c
index 76a9cd3..072daff 100644
--- a/src/soc/intel/elkhartlake/pmutil.c
+++ b/src/soc/intel/elkhartlake/pmutil.c
@@ -259,7 +259,7 @@
/* STM Support */
uint16_t get_pmbase(void)
{
- return (uint16_t) ACPI_BASE_ADDRESS;
+ return (uint16_t)ACPI_BASE_ADDRESS;
}
/*
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index 7ab7ed9a..53df105 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -42,7 +42,7 @@
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */
- setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
+ setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
}
void bootblock_pch_early_init(void)
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index fa63a3d..a247b79 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -51,7 +51,7 @@
/* Use coreboot MP PPI services if Kconfig is enabled */
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
- params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+ params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
mainboard_silicon_init_params(params);
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index 9297ffd..306709d 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -259,7 +259,7 @@
/* STM Support */
uint16_t get_pmbase(void)
{
- return (uint16_t) ACPI_BASE_ADDRESS;
+ return (uint16_t)ACPI_BASE_ADDRESS;
}
/*
diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c
index 4de63f2..20b09f2 100644
--- a/src/soc/intel/jasperlake/bootblock/pch.c
+++ b/src/soc/intel/jasperlake/bootblock/pch.c
@@ -46,7 +46,7 @@
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */
- setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
+ setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
}
void bootblock_pch_early_init(void)
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index a5bcd55..09be260 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -67,7 +67,7 @@
/* Use coreboot MP PPI services if Kconfig is enabled */
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
- params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+ params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
/* Chipset Lockdown */
const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP;
diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c
index f2a4c90..23d5fe7 100644
--- a/src/soc/intel/jasperlake/pmutil.c
+++ b/src/soc/intel/jasperlake/pmutil.c
@@ -259,7 +259,7 @@
/* STM Support */
uint16_t get_pmbase(void)
{
- return (uint16_t) ACPI_BASE_ADDRESS;
+ return (uint16_t)ACPI_BASE_ADDRESS;
}
/*
diff --git a/src/soc/intel/meteorlake/bootblock/soc_die.c b/src/soc/intel/meteorlake/bootblock/soc_die.c
index 58de3619..f5a3c91 100644
--- a/src/soc/intel/meteorlake/bootblock/soc_die.c
+++ b/src/soc/intel/meteorlake/bootblock/soc_die.c
@@ -50,7 +50,7 @@
pci_or_config16(PCI_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */
- setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
+ setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
}
static void soc_die_early_iorange_init(void)
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 9b42b1f..ad6d4bb 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -137,7 +137,7 @@
* Use FSP running MP PPI services to perform CPU feature programming
* if Kconfig is enabled
*/
- s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+ s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
} else {
/* Use coreboot native driver to perform MP init by default */
s_cfg->CpuMpPpi = (uintptr_t)NULL;
diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c
index 974f966..6f35428 100644
--- a/src/soc/intel/meteorlake/pmutil.c
+++ b/src/soc/intel/meteorlake/pmutil.c
@@ -244,7 +244,7 @@
/* STM Support */
uint16_t get_pmbase(void)
{
- return (uint16_t) ACPI_BASE_ADDRESS;
+ return (uint16_t)ACPI_BASE_ADDRESS;
}
/*
diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c
index 6a7f2c2..68e1989 100644
--- a/src/soc/intel/quark/acpi.c
+++ b/src/soc/intel/quark/acpi.c
@@ -72,5 +72,5 @@
{
struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC,
PCI_FUNCTION_NUMBER_QNC_LPC);
- return (uint16_t) pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK;
+ return (uint16_t)pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK;
}
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
index 46671b2..60b7938 100644
--- a/src/soc/intel/quark/memmap.c
+++ b/src/soc/intel/quark/memmap.c
@@ -11,7 +11,7 @@
uintptr_t top_of_low_usable_memory;
/* Locate the top of RAM */
- top_of_low_usable_memory = (uintptr_t) cbmem_top();
+ top_of_low_usable_memory = (uintptr_t)cbmem_top();
top_of_ram = ALIGN_UP(top_of_low_usable_memory, 16 * MiB);
/* Cache postcar and ramstage */
@@ -19,7 +19,7 @@
MTRR_TYPE_WRBACK);
/* Cache RMU area */
- postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory,
+ postcar_frame_add_mtrr(pcf, (uintptr_t)top_of_low_usable_memory,
0x10000, MTRR_TYPE_WRTHROUGH);
/* Cache ESRAM */
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index d120d1e..70d12e4 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -240,7 +240,7 @@
printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax);
}
- params->GraphicsConfigPtr = (u32) vbt_data;
+ params->GraphicsConfigPtr = (u32)vbt_data;
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] =
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index fe26ebf..d411c76 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -136,12 +136,12 @@
/* 4KiB alignment. */
reg32 &= ~0xfff;
- return (void *)(uintptr_t) reg32;
+ return (void *)(uintptr_t)reg32;
}
uintptr_t soc_read_pmc_base(void)
{
- return (uintptr_t) (pmc_mmio_regs());
+ return (uintptr_t)(pmc_mmio_regs());
}
uint32_t *soc_pmc_etr_addr(void)
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index 6186734..d203bda 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -84,9 +84,9 @@
{
msr_t msr;
msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE);
- *prmrr_base = (uint64_t) msr.hi << 32 | msr.lo;
+ *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo;
msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK);
- *prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo;
+ *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo;
return 0;
}
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 9758dba..fc06873 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -56,7 +56,7 @@
pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */
- setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
+ setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN);
}
void bootblock_pch_early_init(void)
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index d7c60be..13c5fc0 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -319,7 +319,7 @@
/* Use coreboot MP PPI services if Kconfig is enabled */
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
- params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+ params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
/* D3Hot and D3Cold for TCSS */
params->D3HotEnable = !config->TcssD3HotDisable;
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c
index 9aca5c2..b8bf975 100644
--- a/src/soc/intel/tigerlake/pmutil.c
+++ b/src/soc/intel/tigerlake/pmutil.c
@@ -268,7 +268,7 @@
/* STM Support */
uint16_t get_pmbase(void)
{
- return (uint16_t) ACPI_BASE_ADDRESS;
+ return (uint16_t)ACPI_BASE_ADDRESS;
}
/*
diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c
index b3ad455..961f908 100644
--- a/src/soc/intel/xeon_sp/cpx/hob_display.c
+++ b/src/soc/intel/xeon_sp/cpx/hob_display.c
@@ -226,7 +226,7 @@
if (hob->type != HOB_TYPE_GUID_EXTENSION)
return;
- guid = (uint8_t *) fsp_hob_header_to_resource(hob);
+ guid = (uint8_t *)fsp_hob_header_to_resource(hob);
if (fsp_guid_compare(guid, fsp_hob_iio_uds_guid))
soc_display_iio_universal_data_hob((const IIO_UDS *)(guid + 16));
diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c
index c31fd61..42b52f3 100644
--- a/src/soc/intel/xeon_sp/nb_acpi.c
+++ b/src/soc/intel/xeon_sp/nb_acpi.c
@@ -49,10 +49,10 @@
for (int e = 0; e < memory_map->numberEntries; ++e) {
const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e];
uint64_t addr =
- (uint64_t) ((uint64_t)mem_element->BaseAddress <<
+ (uint64_t)((uint64_t)mem_element->BaseAddress <<
MEM_ADDR_64MB_SHIFT_BITS);
uint64_t size =
- (uint64_t) ((uint64_t)mem_element->ElementSize <<
+ (uint64_t)((uint64_t)mem_element->ElementSize <<
MEM_ADDR_64MB_SHIFT_BITS);
printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, "
@@ -81,10 +81,10 @@
srat_mem[mmap_index].type = 1; /* Memory affinity structure */
srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t);
- srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff);
- srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32);
- srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff);
- srat_mem[mmap_index].length_high = (uint32_t) (size >> 32);
+ srat_mem[mmap_index].base_address_low = (uint32_t)(addr & 0xffffffff);
+ srat_mem[mmap_index].base_address_high = (uint32_t)(addr >> 32);
+ srat_mem[mmap_index].length_low = (uint32_t)(size & 0xffffffff);
+ srat_mem[mmap_index].length_high = (uint32_t)(size >> 32);
srat_mem[mmap_index].proximity_domain = mem_element->SocketId;
srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED;
if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0)
@@ -335,9 +335,9 @@
unsigned long tmp = current;
printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, "
"End Address (limit): 0x%x\n",
- 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1));
- current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr,
- (uint32_t) ((uint32_t) ptr + size - 1));
+ 0, (uint32_t)ptr, (uint32_t)((uint32_t)ptr + size - 1));
+ current += acpi_create_dmar_rmrr(current, 0, (uint32_t)ptr,
+ (uint32_t)((uint32_t)ptr + size - 1));
printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, "
"PCI Path: 0x%x, 0x%x\n",
@@ -416,7 +416,7 @@
/* SRAT */
current = ALIGN_UP(current, 8);
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
- srat = (acpi_srat_t *) current;
+ srat = (acpi_srat_t *)current;
acpi_create_srat(srat, acpi_fill_srat);
current += srat->header.length;
acpi_add_table(rsdp, srat);
@@ -424,7 +424,7 @@
/* SLIT */
current = ALIGN_UP(current, 8);
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
- slit = (acpi_slit_t *) current;
+ slit = (acpi_slit_t *)current;
acpi_create_slit(slit, acpi_fill_slit);
current += slit->header.length;
acpi_add_table(rsdp, slit);
diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c
index c63285c..3ac5d46 100644
--- a/src/soc/intel/xeon_sp/pmutil.c
+++ b/src/soc/intel/xeon_sp/pmutil.c
@@ -92,12 +92,12 @@
uint8_t *pmc_mmio_regs(void)
{
- return (void *)(uintptr_t) pci_read_config32(PCH_DEV_PMC, PWRMBASE);
+ return (void *)(uintptr_t)pci_read_config32(PCH_DEV_PMC, PWRMBASE);
}
uintptr_t soc_read_pmc_base(void)
{
- return (uintptr_t) (pmc_mmio_regs());
+ return (uintptr_t)(pmc_mmio_regs());
}
uint32_t *soc_pmc_etr_addr(void)
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index 818dd78..0c8e63a 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -277,7 +277,7 @@
const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
- reg &= (uint32_t) ~rst_cpl_mask;
+ reg &= (uint32_t)~rst_cpl_mask;
reg |= val;
/* update BIOS RESET completion bit */