AMD binaryPI: Declare IOAPIC IDs
There is no longer a relation between MAX_CPUS and IOAPIC IDs,
start the cleanup with new declarations.
Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c
index ba34dab..0693a5d 100644
--- a/src/northbridge/amd/pi/00730F01/state_machine.c
+++ b/src/northbridge/amd/pi/00730F01/state_machine.c
@@ -9,6 +9,7 @@
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/nb_common.h>
+#include <southbridge/amd/pi/hudson/ioapic.h>
void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
@@ -64,8 +65,8 @@
* when IOMMU build config is enabled otherwise AGESA will skip
* it during IOMMU init and IVRS generation.
*/
- Late->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1;
- Late->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS;
+ Late->GnbLateConfiguration.GnbIoapicId = GNB_IOAPIC_ID;
+ Late->GnbLateConfiguration.FchIoapicId = FCH_IOAPIC_ID;
}
/* Code for creating CDIT requires hop count table. If it is not