rk3399: Enable bootblock compression
This patch enables the new bootblock compression feature on RK3399,
which requires moving MMU initialization into the decompressor stage and
linking the decompressor (rather than the bootblock) into the entry
point jumped to by the masked ROM.
RK3399's masked ROM seems to be using a bitbang SPI driver to load us
(very long pauses between clocking in each byte), with an effective data
rate of about 1Mbit. Bootblock loading time (as measured on a SPI
analyzer) is reduced by almost 100ms (about a third), while the
decompression time is trivial (under 1ms).
Change-Id: I48967ca5bb51cc4481d69dbacb4ca3c6b96cccea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig
index 7bc923e..1d2960b 100644
--- a/src/soc/rockchip/rk3399/Kconfig
+++ b/src/soc/rockchip/rk3399/Kconfig
@@ -13,6 +13,7 @@
select HAVE_MONOTONIC_TIMER
select UART_OVERRIDE_REFCLK
select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+ select COMPRESS_BOOTBLOCK
if SOC_ROCKCHIP_RK3399
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index 54c5115..b9c3803 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -17,6 +17,9 @@
IDBTOOL = util/rockchip/make_idb.py
+decompressor-y += decompressor.c
+decompressor-y += timer.c
+
bootblock-y += ../common/i2c.c
bootblock-y += ../common/spi.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
@@ -27,7 +30,6 @@
bootblock-y += bootblock.c
bootblock-y += clock.c
bootblock-y += gpio.c
-bootblock-y += mmu_operations.c
bootblock-y += saradc.c
bootblock-y += timer.c
@@ -48,7 +50,6 @@
romstage-y += ../common/spi.c
romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
romstage-y += clock.c
-romstage-y += mmu_operations.c
romstage-y += ../common/pwm.c
romstage-y += timer.c
romstage-y += tsadc.c
diff --git a/src/soc/rockchip/rk3399/bootblock.c b/src/soc/rockchip/rk3399/bootblock.c
index 7b80a75..5265156 100644
--- a/src/soc/rockchip/rk3399/bootblock.c
+++ b/src/soc/rockchip/rk3399/bootblock.c
@@ -34,6 +34,4 @@
/* glb_slv_secure_bypass */
write32(&rk3399_pmusgrf->pmu_slv_con0, 1 << 16 | 1);
-
- rockchip_mmu_init();
}
diff --git a/src/soc/rockchip/rk3399/mmu_operations.c b/src/soc/rockchip/rk3399/decompressor.c
similarity index 96%
rename from src/soc/rockchip/rk3399/mmu_operations.c
rename to src/soc/rockchip/rk3399/decompressor.c
index f1a1371..7d3c714 100644
--- a/src/soc/rockchip/rk3399/mmu_operations.c
+++ b/src/soc/rockchip/rk3399/decompressor.c
@@ -21,7 +21,7 @@
#include <soc/mmu_operations.h>
#include <symbols.h>
-void rockchip_mmu_init(void)
+void decompressor_soc_init(void)
{
mmu_init();
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index 04ffce6..e181a35 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -31,8 +31,9 @@
SRAM_START(0xFF8C0000)
PRERAM_CBFS_CACHE(0xFF8C0000, 7K)
TIMESTAMP(0xFF8C1C00, 1K)
- BOOTBLOCK(0xFF8C2004, 36K - 4)
- OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CB000, 92K)
+ /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */
+ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4)
+ BOOTBLOCK(0xFF8D8000, 40K)
VBOOT2_WORK(0XFF8E2000, 12K)
TTB(0xFF8E5000, 24K)
PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K)
diff --git a/src/soc/rockchip/rk3399/include/soc/mmu_operations.h b/src/soc/rockchip/rk3399/include/soc/mmu_operations.h
index d8a6016..5f06a45 100644
--- a/src/soc/rockchip/rk3399/include/soc/mmu_operations.h
+++ b/src/soc/rockchip/rk3399/include/soc/mmu_operations.h
@@ -26,5 +26,4 @@
UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC,
};
-void rockchip_mmu_init(void);
#endif