tree 16f6a9887c64ae65376692e79d03cc668a5a2ca1
parent 2874330828fa6950bccba04872dbfc8cfae91d99
author Kyösti Mälkki <kyosti.malkki@gmail.com> 1561917607 +0300
committer Kyösti Mälkki <kyosti.malkki@gmail.com> 1562223127 +0000

drivers/intel/fsp1_1: Adjust postcar MTRRs

Use of romstage_ram_stack_bottom() was invalid, it
potentially uses a different ROMSTAGE_RAM_STACK_SIZE
from the postcar_frame_init() call.

If alignment evaluated to 1 MiB, that WB MTRR may not
have covered all of CBMEM range, having some impact
on boot speeds.

There is no need to accurately describe write-back
MTRR ranges for postcar.

Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>