commit | e3eedf7548f282549d272d4e9b352dfb6e3b80da | [log] [tgz] |
---|---|---|
author | Karthikeyan Ramasubramanian <kramasub@google.com> | Thu Jul 14 15:37:07 2022 -0600 |
committer | Martin L Roth <gaumless@tutanota.com> | Wed Jul 20 14:14:30 2022 +0000 |
tree | d0eb32dd51d04b13b4fd5f3c0c5c7a1e2e8ad33b | |
parent | df74de1cac679549b515ed5f4eb86e7229ab53cc [diff] |
soc/amd/common/psp_verstage: Fix update_boot_region On SoCs where PSP use A/B recovery layout, PSP expects PSP L2 directory address relative to the start of the SPI ROM. Unfortunately there is nothing in the EFS2 header to help identify such SoCs. Hence add a config item to statically identify such SoCs. Also when PSP uses A/B recovery layout, BIOS L2 directory is an entry in the PSP L2 directory. Hence the address of BIOS L2 directory is not part of EFS2 header. Thankfully PSP is able to identify the BIOS L2 directory itself and does not expect PSP verstage to pass the address. Modify PSP verstage to handle these updates. BUG=b:217414563 TEST=Build Skyrim BIOS image. Ensure that PSP verstage returned the PSP L2 directory as expected. Change-Id: I2f856a62055c80b8e2db91c983832611a5f0389c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.