sandybridge/gma_lvds: support both Sandy&Ivy on one board
Sandy and Ivy Bridge processors use the same socket, and a mainboard
with the socket can support both types of CPUs. However, they use
different native graphics init code for LVDS and cause a crash if
running the wrong code.
This change detects the CPU type and then selects the right code to
run. It will add some more code in ramstage. It also merges the
{SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS.
Tested on a Lenovo T520 with i7-2630qm and i7-3720qm
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91
Reviewed-on: https://review.coreboot.org/12087
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index f435f85..9b90f36 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -51,12 +51,7 @@
int
default 512
-config IVYBRIDGE_LVDS
- def_bool n
- select MAINBOARD_HAS_NATIVE_VGA_INIT
- select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
-
-config SANDYBRIDGE_LVDS
+config SANDYBRIDGE_IVYBRIDGE_LVDS
def_bool n
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index a58d9b1..4a7a854 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -18,8 +18,8 @@
ramstage-y += ram_calc.c
ramstage-y += northbridge.c
ramstage-y += gma.c
-ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c
-ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_sandybridge_lvds.c
+ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c
+ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c
ramstage-y += acpi.c
ramstage-y += mrccache.c
diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h
index 0832468..534b42e 100644
--- a/src/northbridge/intel/sandybridge/gma.h
+++ b/src/northbridge/intel/sandybridge/gma.h
@@ -117,5 +117,7 @@
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u32 physbase, u16 pio, u8 *mmio, u32 lfb);
+int i915lightup_ivy(const struct i915_gpu_controller_info *info,
+ u32 physbase, u16 pio, u8 *mmio, u32 lfb);
#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index 1d7611f..f6818dd 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -153,8 +153,8 @@
read32(mmio + 0xc4000);
}
-int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
+int i915lightup_ivy(const struct i915_gpu_controller_info *info,
+ u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
{
int i;
u8 edid_data[128];
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index e18f146..3b4b64c 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -24,6 +24,7 @@
#include <drivers/intel/gma/i915.h>
#include "gma.h"
#include "chip.h"
+#include "sandybridge.h"
#include <pc80/vga.h>
#include <pc80/vga_io.h>
#include <device/pci_def.h>
@@ -142,6 +143,10 @@
if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
return 0;
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ return i915lightup_ivy(info, physbase, piobase, mmio, lfb);
+ }
+
write32(mmio + 0x00070080, 0x00000000);
write32(mmio + DSPCNTR(0), 0x00000000);
write32(mmio + 0x00071180, 0x00000000);