arch/riscv: Refactor bootblock.S
A few things are currently missing:
- The trap handler doesn't set the stack pointer, which can easily
result in trap loops or memory corruptions.
- The SBI trampolin page (as described in version 1.9 of the RISC-V
Privileged Architecture Specification), has been removed for now.
Signed-off-by: Jonathan Neuschäfer <email@example.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <firstname.lastname@example.org>
diff --git a/src/arch/riscv/id.S b/src/arch/riscv/id.S
new file mode 100644
@@ -0,0 +1,33 @@
+ * This file is part of the coreboot project.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ .section ".id", "a", %progbits
+ .globl __id_start
+ .asciz "1" //COREBOOT_VERSION
+ .asciz "ucb" //CONFIG_MAINBOARD_VENDOR
+ .asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
+.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */
+.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */
+.long CONFIG_ROM_SIZE /* Size of this romimage */
+ .globl __id_end