| commit | 8e0bbb30b616fe65bb03186220753af76dfda7d2 | [log] [tgz] |
|---|---|---|
| author | Felix Held <felix-coreboot@felixheld.de> | Mon Jul 17 22:57:33 2023 +0200 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Tue Jul 18 21:51:22 2023 +0000 |
| tree | 60e00ba31e1ce7398796c6810cb27cd0573089cf | |
| parent | b2de1a336855a4900245c7951c938e314f68b897 [diff] |
soc/amd/stoneyridge/pstate_util: fix off by one in P-state MSR number There are 8 P-state MSRs and not only 7. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic2899b6e454233c6cbb8fc1e439ff069c4d3d3a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
diff --git a/src/soc/amd/stoneyridge/pstate_util.c b/src/soc/amd/stoneyridge/pstate_util.c index 097a913..12bc2b5 100644 --- a/src/soc/amd/stoneyridge/pstate_util.c +++ b/src/soc/amd/stoneyridge/pstate_util.c
@@ -21,7 +21,7 @@ bool first = true; uint32_t frequency_id; - for (i = 0; i < 7; i++) { + for (i = 0; i < 8; i++) { pstate_reg.raw = rdmsr(PSTATE_MSR(i)).raw; if (!pstate_reg.pstate_en)