superio/fintek: Improve code formatting

Change-Id: I5ae2a2da1994fcc587540586d7404ebf18eb2ca0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h
index d038c3d..e4e2f27 100644
--- a/src/superio/fintek/f71869ad/f71869ad.h
+++ b/src/superio/fintek/f71869ad/f71869ad.h
@@ -5,15 +5,15 @@
 #define SUPERIO_FINTEK_F71869AD_H
 
 /* Logical Device Numbers (LDN). */
-#define F71869AD_FDC    0x00	/* Floppy */
-#define F71869AD_SP1    0x01	/* UART1 */
-#define F71869AD_SP2    0x02	/* UART2 */
-#define F71869AD_PP     0x03	/* Parallel port */
-#define F71869AD_HWM    0x04	/* Hardware monitor */
-#define F71869AD_KBC    0x05	/* PS/2 keyboard and mouse */
-#define F71869AD_GPIO   0x06	/* General Purpose I/O (GPIO) */
-#define F71869AD_WDT    0x07	/* WDT */
-#define F71869AD_CIR    0x08	/* CIR */
-#define F71869AD_PME    0x0a	/* Power Management Events (PME) and ACPI */
+#define F71869AD_FDC	0x00	/* Floppy */
+#define F71869AD_SP1	0x01	/* UART1 */
+#define F71869AD_SP2	0x02	/* UART2 */
+#define F71869AD_PP	0x03	/* Parallel port */
+#define F71869AD_HWM	0x04	/* Hardware monitor */
+#define F71869AD_KBC	0x05	/* PS/2 keyboard and mouse */
+#define F71869AD_GPIO	0x06	/* General Purpose I/O (GPIO) */
+#define F71869AD_WDT	0x07	/* WDT */
+#define F71869AD_CIR	0x08	/* CIR */
+#define F71869AD_PME	0x0a	/* Power Management Events (PME) and ACPI */
 
 #endif /* SUPERIO_FINTEK_F71869AD_H */
diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h
index 865cecb..0c8463e 100644
--- a/src/superio/fintek/f81216h/f81216h.h
+++ b/src/superio/fintek/f81216h/f81216h.h
@@ -7,11 +7,11 @@
 #include <device/pnp_type.h>
 
 /* Logical Device Numbers (LDN). */
-#define F81216H_SP1    0x00	/* UART1 (+CIR mode) */
-#define F81216H_SP2    0x01	/* UART2 */
-#define F81216H_SP3    0x02	/* UART3 */
-#define F81216H_SP4    0x03	/* UART4 */
-#define F81216H_WDT    0x08	/* WDT   */
+#define F81216H_SP1	0x00	/* UART1 (+CIR mode) */
+#define F81216H_SP2	0x01	/* UART2 */
+#define F81216H_SP3	0x02	/* UART3 */
+#define F81216H_SP4	0x03	/* UART4 */
+#define F81216H_WDT	0x08	/* WDT   */
 
 /**
  * The PNP config entry key is parameterised
diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl
index 0887d6a..3065458 100644
--- a/src/superio/fintek/f81803a/acpi/superio.asl
+++ b/src/superio/fintek/f81803a/acpi/superio.asl
@@ -237,13 +237,13 @@
 	{
 		Offset(0x00), /*Control Reg 5 */
 		, 7,
-		PSIN, 1 /* PSIN_FLAG  */
+		PSIN, 1 /* PSIN_FLAG */
 	}
 
 	/* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */
 	Method(CPSI, 0, Serialized)
 	{
-		/*   DBG0("SIO CPSI")*/
+		/* DBG0("SIO CPSI") */
 		ENTER_CONFIG_MODE(SUPERIO_PME_LDN)
 		Store(1, PSIN)
 		EXIT_CONFIG_MODE()
diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h
index fdf9ecf..9cd720f 100644
--- a/src/superio/fintek/f81803a/f81803a.h
+++ b/src/superio/fintek/f81803a/f81803a.h
@@ -19,7 +19,7 @@
   #define F81803A_WDT			0x07	/* Watch Dog Timer */
   #define F81803A_PME			0x0a	/* Power Management Events (PME) */
 
-/*  Global Control Registers */
+/* Global Control Registers */
 #define CLOCK_SELECT_REG		0x26
 #define   FUNC_PROG_SELECT		(1<<3)
 #define PORT_SELECT_REG			0x27
diff --git a/src/superio/fintek/f81803a/fan_control.c b/src/superio/fintek/f81803a/fan_control.c
index 3b01a64..2143f2e 100644
--- a/src/superio/fintek/f81803a/fan_control.c
+++ b/src/superio/fintek/f81803a/fan_control.c
@@ -128,7 +128,7 @@
 	u8 current_value, i;
 	for (i = 0; i < count; i++) {
 		current_value = values[i];
-		if (current_value  > CPU_DAMAGE_TEMP)
+		if (current_value > CPU_DAMAGE_TEMP)
 			return STATUS_INVALID_VALUE;
 		if (current_value >= last_value)
 			return STATUS_INVALID_ORDER;
diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c
index e6333f5..3d3a301 100644
--- a/src/superio/fintek/f81866d/f81866d_hwm.c
+++ b/src/superio/fintek/f81866d/f81866d_hwm.c
@@ -14,29 +14,29 @@
 
 /* Register addresses */
 // Choose between AMD and Intel
-#define HWM_AMD_TSI_ADDR             0x08
-#define HWM_AMD_TSI_CONTROL_REG      0x0A
+#define HWM_AMD_TSI_ADDR		0x08
+#define HWM_AMD_TSI_CONTROL_REG		0x0A
 
 // Set temp sensors type
-#define TEMP_SENS_TYPE_REG	0x6B
+#define TEMP_SENS_TYPE_REG		0x6B
 
 // FAN prog sel
-#define HWM_FAN3_CONTROL	0x9A
-#define HWM_FAN_SEL		0x94
-#define HWM_FAN_MODE		0x96
-#define HWM_FAN2_TEMP_MAP_SEL      0xBF
+#define HWM_FAN3_CONTROL		0x9A
+#define HWM_FAN_SEL			0x94
+#define HWM_FAN_MODE			0x96
+#define HWM_FAN2_TEMP_MAP_SEL		0xBF
 
 // Fan 2 - 4 Boundaries
-#define HWM_FAN2_BOUND1	0xB6
-#define HWM_FAN2_BOUND2	0xB7
-#define HWM_FAN2_BOUND3	0xB8
-#define HWM_FAN2_BOUND4	0xB9
+#define HWM_FAN2_BOUND1			0xB6
+#define HWM_FAN2_BOUND2			0xB7
+#define HWM_FAN2_BOUND3			0xB8
+#define HWM_FAN2_BOUND4			0xB9
 // Fan 2 - 5 Segment speeds
-#define HWM_FAN2_SEG1_SPEED_COUNT  0xBA
-#define HWM_FAN2_SEG2_SPEED_COUNT  0xBB
-#define HWM_FAN2_SEG3_SPEED_COUNT  0xBC
-#define HWM_FAN2_SEG4_SPEED_COUNT  0xBD
-#define HWM_FAN2_SEG5_SPEED_COUNT  0xBE
+#define HWM_FAN2_SEG1_SPEED_COUNT	0xBA
+#define HWM_FAN2_SEG2_SPEED_COUNT	0xBB
+#define HWM_FAN2_SEG3_SPEED_COUNT	0xBC
+#define HWM_FAN2_SEG4_SPEED_COUNT	0xBD
+#define HWM_FAN2_SEG5_SPEED_COUNT	0xBE
 
 
 void f81866d_hwm_init(struct device *dev)
diff --git a/src/superio/fintek/f81866d/f81866d_uart.c b/src/superio/fintek/f81866d/f81866d_uart.c
index c6c1889..9590dc4 100644
--- a/src/superio/fintek/f81866d/f81866d_uart.c
+++ b/src/superio/fintek/f81866d/f81866d_uart.c
@@ -36,13 +36,13 @@
 	pnp_write_config(dev, PORT_SELECT_REGISTER, tmp & 0xFE);
 
 	// Set UART 3 function (Bit 4/5), otherwise pin 36-43 are GPIO
-	if (dev->path.pnp.device ==  F81866D_SP3) {
+	if (dev->path.pnp.device == F81866D_SP3) {
 		tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG);
 		pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0x30);
 	}
 
 	// Set UART 4 function (Bit 6/7), otherwise pin 44-51 are GPIO
-	if (dev->path.pnp.device ==  F81866D_SP4) {
+	if (dev->path.pnp.device == F81866D_SP4) {
 		tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG);
 		pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xC0);
 	}