soc/intel/xeon_sp/util: Locate PCU by PCI device ID
Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Change-Id: I1dcad4ba3fbc0295d74e1bf832cce95f014fd7bf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80095
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index 8658e01..7fc903a 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -6,9 +6,11 @@
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ids.h>
#include <intelblocks/cfg.h>
#include <intelblocks/cpulib.h>
#include <intelpch/lockdown.h>
+#include <soc/chip_common.h>
#include <soc/pci_devs.h>
#include <soc/msr.h>
#include <soc/soc_util.h>
@@ -120,19 +122,20 @@
#if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */
/* return true if command timed out else false */
-static bool wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask,
- uint32_t target)
+static bool wait_for_bios_cmd_cpl(struct device *pcu1, uint32_t reg, uint32_t mask,
+ uint32_t target)
{
const uint32_t max_delay = 5000; /* 5 seconds max */
const uint32_t step_delay = 50; /* 50 us */
struct stopwatch sw;
stopwatch_init_msecs_expire(&sw, max_delay);
- while ((pci_s_read_config32(dev, reg) & mask) != target) {
+ while ((pci_read_config32(pcu1, reg) & mask) != target) {
udelay(step_delay);
if (stopwatch_expired(&sw)) {
- printk(BIOS_ERR, "%s timed out for dev: %x, reg: 0x%x, "
- "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target);
+ printk(BIOS_ERR, "%s timed out for dev: %s, reg: 0x%x, "
+ "mask: 0x%x, target: 0x%x\n",
+ __func__, dev_path(pcu1), reg, mask, target);
return true; /* timedout */
}
}
@@ -140,94 +143,94 @@
}
/* return true if command timed out else false */
-static bool write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data)
+static bool write_bios_mailbox_cmd(struct device *pcu1, uint32_t command, uint32_t data)
{
/* verify bios is not in busy state */
- if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0))
+ if (wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0))
return true; /* timed out */
/* write data to data register */
- printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%x\n", __func__,
- PCU_CR1_BIOS_MB_DATA_REG, data);
- pci_s_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data);
+ printk(BIOS_SPEW, "%s - pci_write_config32 reg: 0x%x, data: 0x%x\n", __func__,
+ PCU_CR1_BIOS_MB_DATA_REG, data);
+
+ pci_write_config32(pcu1, PCU_CR1_BIOS_MB_DATA_REG, data);
/* write the command */
- printk(BIOS_SPEW, "%s - pci_s_write_config32 reg: 0x%x, data: 0x%lx\n", __func__,
- PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK);
- pci_s_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
- command | BIOS_MB_RUN_BUSY_MASK);
+ printk(BIOS_SPEW, "%s - pci_write_config32 reg: 0x%x, data: 0x%lx\n", __func__,
+ PCU_CR1_BIOS_MB_INTERFACE_REG, command | BIOS_MB_RUN_BUSY_MASK);
+
+ pci_write_config32(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG,
+ command | BIOS_MB_RUN_BUSY_MASK);
/* wait for completion or time out*/
- return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
- BIOS_MB_RUN_BUSY_MASK, 0);
+ return wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_MB_INTERFACE_REG,
+ BIOS_MB_RUN_BUSY_MASK, 0);
}
/* return true if command timed out else false */
-static bool set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
- uint32_t pcode_init_mask, uint32_t val)
+static bool set_bios_reset_cpl_for_package(struct device *pcu1,
+ uint32_t rst_cpl_mask,
+ uint32_t pcode_init_mask,
+ uint32_t val)
{
- const uint32_t bus = get_socket_ubox_busno(socket);
- const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
-
- uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
- reg &= (uint32_t)~rst_cpl_mask;
- reg |= val;
-
/* update BIOS RESET completion bit */
- pci_s_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg);
+ pci_update_config32(pcu1, PCU_CR1_BIOS_RESET_CPL_REG, ~rst_cpl_mask, val);
/* wait for PCU ack */
- return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask,
- pcode_init_mask);
+ return wait_for_bios_cmd_cpl(pcu1, PCU_CR1_BIOS_RESET_CPL_REG,
+ pcode_init_mask, pcode_init_mask);
}
static void set_bios_init_completion_for_package(uint32_t socket)
{
+ struct device *pcu0 = dev_find_device_on_socket(socket, PCI_VID_INTEL, PCU_CR0_DEVID);
+ struct device *pcu1 = dev_find_device_on_socket(socket, PCI_VID_INTEL, PCU_CR1_DEVID);
uint32_t data;
bool timedout;
- const uint32_t bus = get_socket_ubox_busno(socket);
- const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
+
+ if (!pcu0 || !pcu1)
+ die("Failed to locate PCU PCI device\n");
/* read PCU config */
- timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
+ timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_READ_PCU_MISC_CFG, 0);
if (timedout) {
/* 2nd try */
- timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
+ timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_READ_PCU_MISC_CFG, 0);
if (timedout)
die("BIOS PCU Misc Config Read timed out.\n");
/* Since the 1st try failed, we need to make sure PCU is in stable state */
- data = pci_s_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG);
- printk(BIOS_SPEW, "%s - pci_s_read_config32 reg: 0x%x, data: 0x%x\n",
+ data = pci_read_config32(pcu1, PCU_CR1_BIOS_MB_DATA_REG);
+ printk(BIOS_SPEW, "%s - pci_read_config32 reg: 0x%x, data: 0x%x\n",
__func__, PCU_CR1_BIOS_MB_DATA_REG, data);
- timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data);
+ timedout = write_bios_mailbox_cmd(pcu1, BIOS_CMD_WRITE_PCU_MISC_CFG, data);
if (timedout)
die("BIOS PCU Misc Config Write timed out.\n");
}
/* update RST_CPL3, PCODE_INIT_DONE3 */
- timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK,
+ timedout = set_bios_reset_cpl_for_package(pcu1, RST_CPL3_MASK,
PCODE_INIT_DONE3_MASK, RST_CPL3_MASK);
if (timedout)
die("BIOS RESET CPL3 timed out.\n");
/* Set PMAX_LOCK - must be set before RESET CPL4 */
- data = pci_s_read_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX);
+ data = pci_read_config32(pcu0, PCU_CR0_PMAX);
data |= PMAX_LOCK;
- pci_s_write_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX, data);
+ pci_write_config32(pcu0, PCU_CR0_PMAX, data);
/* update RST_CPL4, PCODE_INIT_DONE4 */
- timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK,
+ timedout = set_bios_reset_cpl_for_package(pcu1, RST_CPL4_MASK,
PCODE_INIT_DONE4_MASK, RST_CPL4_MASK);
if (timedout)
die("BIOS RESET CPL4 timed out.\n");
/* set CSR_DESIRED_CORES_CFG2 lock bit */
- data = pci_s_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG);
+ data = pci_read_config32(pcu1, PCU_CR1_DESIRED_CORES_CFG2_REG);
data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK;
- printk(BIOS_SPEW, "%s - pci_s_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n",
+ printk(BIOS_SPEW, "%s - pci_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n",
__func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
- pci_s_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
+ pci_write_config32(pcu1, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
}
void set_bios_init_completion(void)