- Minor mod to reset16.inc to work with newer binutils hopefully this works with older ones...
- Update apic.h to include the APIC_TASK_PRI register definition
- Update mptable.c to have a reasonable board OEM and productid
- Additional testfiles for romcc.
- Split out auto.c and early failover.c moving their generic bits elsewere
- Enable cache of the rom
- Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/util/romcc/tests/simple_test32.c b/util/romcc/tests/simple_test32.c
new file mode 100644
index 0000000..bd6947a
--- /dev/null
+++ b/util/romcc/tests/simple_test32.c
@@ -0,0 +1,35 @@
+void main(void)
+{
+ unsigned long addr, start, stop;
+ start = 0x00100000;
+ stop = 0x00180000;
+
+
+ for(addr = start; addr < stop ;) {
+ unsigned char ch;
+ const char *str = "\r";
+ while((ch = *str++) != '\0') {
+ while(__builtin_inb(0x3f))
+ ;
+ __builtin_outb(ch, 0x3f8);
+
+ while(__builtin_inb(0x3f))
+ ;
+ }
+ asm (
+ "jmp 2f\n\t"
+ "1:\n\t"
+ "testl $0xffff, %0\n\t"
+ "jz 3f\n\t"
+ "movnti %0, (%0)\n\t"
+ "add $4, %0\n\t"
+ "2:\n\t"
+ "cmp %2, %0\n\t"
+ "jl 1b\n\t"
+ "3:\n\t"
+ : "=b" (addr) /* outputs */
+ : "0" (addr), "r" (stop) /* intputs */
+ : /* clobbers */
+ );
+ };
+}