include/console: Rename and update POST_ENTRY_RAMSTAGE postcode
Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f
to make the ramstage postcodes appear in an incremental order.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c
index 895a942..cd4a57e 100644
--- a/src/lib/hardwaremain.c
+++ b/src/lib/hardwaremain.c
@@ -442,7 +442,7 @@
cbmem_initialize();
timestamp_add_now(TS_START_RAMSTAGE);
- post_code(POST_ENTRY_RAMSTAGE);
+ post_code(POST_ENTRY_HARDWAREMAIN);
/* Handoff sleep type from romstage. */
acpi_is_wakeup_s3();