diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 4cd2839..d2f5b7c 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -304,7 +304,7 @@
 	u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
 
 	printk(BIOS_DEBUG, "PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
-			   "postdiv2=%d, vco=%u khz, output=%u khz\n",
+			   "postdiv2=%d, vco=%u kHz, output=%u kHz\n",
 			   pll_con, div->fbdiv, div->refdiv, div->postdiv1,
 			   div->postdiv2, vco_khz, output_khz);
 	assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
@@ -485,7 +485,7 @@
 
 	/* some cru registers changed by bootrom, we'd better reset them to
 	 * reset/default values described in TRM to avoid confusion in kernel.
-	 * Please consider these threee lines as a fix of bootrom bug.
+	 * Please consider these three lines as a fix of bootrom bug.
 	 */
 	write32(&cru_ptr->clksel_con[12], 0xffff4101);
 	write32(&cru_ptr->clksel_con[19], 0xffff033f);