soc/intel/meteorlake: Set TCC to 90°C
Set tcc_offset value to 20 in chipset for Thermal Control
Circuit (TCC) activation feature for meteorlake silicon.
Also, remove tcc_offset default value from rex baseboard
and variants.
BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board
Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 76b9dcd..1b37784 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -36,9 +36,6 @@
# DPTF enable
register "dptf_enable" = "1"
- # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20)
- register "tcc_offset" = "20"
-
# Enable CNVi BT
register "cnvi_bt_core" = "true"
diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb
index c43c09f..1cc0530 100644
--- a/src/mainboard/google/rex/variants/screebo/overridetree.cb
+++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb
@@ -64,9 +64,6 @@
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
- # Temporary setting TCC of 90C = Tj max - Tcc
- register "tcc_offset" = "20"
-
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb
index 1f68eff..59eb2c9 100644
--- a/src/soc/intel/meteorlake/chipset.cb
+++ b/src/soc/intel/meteorlake/chipset.cb
@@ -19,6 +19,9 @@
# putting it under register "common_soc_config" in overridetree.cb file.
register "common_soc_config.pch_thermal_trip" = "130"
+ # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20)
+ register "tcc_offset" = "20"
+
# Enable CNVi WiFi
register "cnvi_wifi_core" = "true"