mb/google/dedede: Remove pad termination for RAM_STRAP_4
The stuffed resistor straps are weaker compared to the internal pull-up.
This can cause the GPIO to read '1' always. Remove the internal pull-up.
Also read the GPIO only on the boards where the board version is
populated.
BUG=b:154301008
TEST=Build and boot the mainboard.
Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c
index 2efaaf1..7a700f4 100644
--- a/src/mainboard/google/dedede/romstage.c
+++ b/src/mainboard/google/dedede/romstage.c
@@ -18,7 +18,7 @@
.read_type = READ_SPD_CBFS,
.spd_spec.spd_index = variant_memory_sku(),
};
- bool half_populated = !gpio_get(GPIO_MEM_CH_SEL);
+ bool half_populated = variant_mem_is_half_populated();
memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated);
}
diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c
index b09d6c1..6adb35b 100644
--- a/src/mainboard/google/dedede/variants/baseboard/gpio.c
+++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c
@@ -348,7 +348,7 @@
/* S0 : RAM_STRAP_4 */
- PAD_CFG_GPI(GPP_S0, UP_5K, DEEP),
+ PAD_CFG_GPI(GPP_S0, NONE, DEEP),
/* S1 : RSVD_STRAP */
PAD_NC(GPP_S1, NONE),
/* S2 : DMIC1_CLK */
@@ -418,7 +418,7 @@
PAD_CFG_GPO(GPP_H19, 0, DEEP),
/* S0 : RAM_STRAP_4 */
- PAD_CFG_GPI(GPP_S0, UP_5K, DEEP),
+ PAD_CFG_GPI(GPP_S0, NONE, DEEP),
};
const struct pad_config *__weak variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
index 8fd5119..48c1419 100644
--- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
@@ -33,4 +33,11 @@
/* Return memory SKU for the variant */
int variant_memory_sku(void);
+/**
+ * Get data whether memory channel is half-populated or not
+ *
+ * @return false on boards where memory channel is half-populated, true otherwise.
+ */
+bool variant_mem_is_half_populated(void);
+
#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/dedede/variants/baseboard/memory.c b/src/mainboard/google/dedede/variants/baseboard/memory.c
index 08c3bde..120cb4e 100644
--- a/src/mainboard/google/dedede/variants/baseboard/memory.c
+++ b/src/mainboard/google/dedede/variants/baseboard/memory.c
@@ -70,3 +70,8 @@
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}
+
+bool __weak variant_mem_is_half_populated(void)
+{
+ return !gpio_get(GPIO_MEM_CH_SEL);
+}
diff --git a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc
index fb9b4f4..d3d6452 100644
--- a/src/mainboard/google/dedede/variants/waddledee/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/waddledee/Makefile.inc
@@ -7,3 +7,5 @@
SPD_SOURCES = Micron_MT53E512M32D2NP_2GB #0b0000
SPD_SOURCES += empty #0b0001
+
+romstage-y += memory.c
diff --git a/src/mainboard/google/dedede/variants/waddledee/memory.c b/src/mainboard/google/dedede/variants/waddledee/memory.c
new file mode 100644
index 0000000..d1e8af2
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/waddledee/memory.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+
+bool variant_mem_is_half_populated(void)
+{
+ uint32_t board_ver;
+
+ /* On boards where board version is populated, ram strap is also populated */
+ if (!google_chromeec_get_board_version(&board_ver))
+ return !gpio_get(GPIO_MEM_CH_SEL);
+
+ return false;
+}
diff --git a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc
index 71042c0..75cbb6a 100644
--- a/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc
+++ b/src/mainboard/google/dedede/variants/waddledoo/Makefile.inc
@@ -7,3 +7,5 @@
SPD_SOURCES = empty #0b0000
SPD_SOURCES += Micron_MT53E512M32D2NP_2GB #0b0001
+
+romstage-y += memory.c
diff --git a/src/mainboard/google/dedede/variants/waddledoo/memory.c b/src/mainboard/google/dedede/variants/waddledoo/memory.c
new file mode 100644
index 0000000..d1e8af2
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/waddledoo/memory.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+
+bool variant_mem_is_half_populated(void)
+{
+ uint32_t board_ver;
+
+ /* On boards where board version is populated, ram strap is also populated */
+ if (!google_chromeec_get_board_version(&board_ver))
+ return !gpio_get(GPIO_MEM_CH_SEL);
+
+ return false;
+}