commit 8c905a82f5d07ae7936114d392ec897756c0df9d
author Elyes HAOUAS <ehaouas@noos.fr> Thu Feb 07 09:00:47 2019 +0100
committer Patrick Georgi <pgeorgi@google.com> Fri Feb 08 11:00:01 2019 +0000
tree 51da94b62ccb1acb79e74ea71e7a7201b6ea91a2
parent d5c458f98ad71f66815f637c5cb6305adc133b27

mb/{asrock,intel,kontron}: Include missing <arch/io.h>

Also includes lines sorted

Change-Id: Idf2b41f471f531b2a9c3e620563e3c658dea4729
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31267
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/asrock/g41c-gs/romstage.c

diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 0605ef1..ab6b1d8 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -15,17 +15,18 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/io.h>
 #include <console/console.h>
-#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/gpio.h>
-#include <northbridge/intel/x4x/x4x.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
-#include <superio/nuvoton/nct6776/nct6776.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/nuvoton/common/nuvoton.h>
+#include <cpu/x86/bist.h>
 #include <northbridge/intel/x4x/iomap.h>
+#include <northbridge/intel/x4x/x4x.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
 
 #define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)
 #define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)

src/mainboard/asus/p5qpl-am/romstage.c

diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index abe3b67..7f84b6a 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -15,18 +15,19 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/io.h>
 #include <console/console.h>
-#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/gpio.h>
-#include <northbridge/intel/x4x/x4x.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
-#include <superio/winbond/common/winbond.h>
-#include <northbridge/intel/x4x/iomap.h>
-#include <halt.h>
 #include <cpu/intel/speedstep.h>
+#include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
+#include <halt.h>
+#include <northbridge/intel/x4x/iomap.h>
+#include <northbridge/intel/x4x/x4x.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)

src/mainboard/intel/dg41wv/romstage.c

diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index 7038538..2caf5ec 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -15,15 +15,16 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/io.h>
 #include <console/console.h>
-#include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/gpio.h>
-#include <northbridge/intel/x4x/x4x.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
-#include <superio/winbond/common/winbond.h>
+#include <cpu/x86/bist.h>
 #include <northbridge/intel/x4x/iomap.h>
+#include <northbridge/intel/x4x/x4x.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627dhg/w83627dhg.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
 #define LPC_DEV PCI_DEV(0, 0x1f, 0)

src/mainboard/kontron/ktqm77/romstage.c

diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 9083764..ea93e05 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -16,18 +16,20 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <timestamp.h>
-#include <device/pci_def.h>
-#include <cpu/x86/lapic.h>
 #include <arch/acpi.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/raminit.h>
+#include <arch/io.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/msr.h>
+#include <device/pci_def.h>
+#include <halt.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <cpu/x86/msr.h>
-#include <halt.h>
 #include <superio/winbond/common/winbond.h>
+#include <timestamp.h>
+
 
 void pch_enable_lpc(void)
 {